Abstract: A semiconductor device, a manufacturing method thereof and an operating method thereof are provided. The semiconductor device includes a substrate, a first well, a second well, a first heavily doping region, a second heavily doping region, a third heavily doping region, and an electrode layer. The first and the second wells are disposed on the substrate. The first and the third heavily doping regions, which are separated from each other, are disposed in the first well, and the second heavily doping region is disposed in the second well. The electrode layer is disposed on the first well. Each of the second well, the first heavily doping region, and the second heavily doping region has a first type doping. Each of the substrate, the first well, and the third heavily doping region has a second type doping, which is complementary to the first type doping.

Abstract: A memory expansion assembly includes a first plate having first electrical slots and a first electrically connecting portion, a second plate pivotally connected to the first plate and having second electrical slots and a second electrically connecting portion, a first engaging assembly, and a second engaging assembly. The first electrical slots are electrically connected to the first electrically connecting portion. The second electrical slots are electrically connected to the second electrically connecting portion. The second plate is adapted to pivot relative to the first plate to have a folded position when the two are close to each other and an unfolded position when the two are away from each other. The first engaging assembly is disposed on a side of the first plate. The second engaging assembly is disposed on a side of the second plate. The first engaging assembly is removably engaged with the second engaging assembly.

Abstract: A memory combination is applied in a computer system. The computer system includes a motherboard. The motherboard includes a first riser slot and a second riser slot disposed side by side. The memory combination includes a first riser board and a second riser board. The first riser board is plugged into the first riser slot and includes a plurality of first memory sockets. The second riser board is plugged into the second riser slot and includes a plurality of second memory sockets. The first memory sockets face the second riser board, and the second memory sockets face the first riser board. The first memory sockets are unaligned with the second memory sockets.

Abstract: A memory combination includes a first riser board, a second riser board, and a pivotal plate. The first riser hoard includes a plurality of first memory sockets of which long axis directions are parallel to each other. The second riser board includes a plurality of second memory sockets of which long axis directions are parallel to each other. Two end of the pivotal plate are pivotally connected to the first riser board and the second riser board based on an axial direction respectively. When the first and second riser boards rotate to be perpendicular to the pivotal plate, the first memory sockets face the second riser board, and the second memory sockets face the first riser board. The axial direction is perpendicular to the long axis directions of the first memory sockets and the long axis directions of the second memory sockets.

Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.

Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates.

Abstract: A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

Abstract: A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.

Abstract: A bi-directional triode thyristor (TRIAC) device for high voltage electrostatic discharge (ESD) protection may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates. The portion of the N-type well region that is interposed between the two P-type well regions may comprise one or more P-type portions, such as a P+ doped plate or a P-type implant.

Abstract: A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

Abstract: A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.

Abstract: A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.

Abstract: A semiconductor structure and a manufacturing method and an operating method for the same are provided. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, an anode, and a cathode. The second well region is adjacent to the first well region. The first doped region is on the second well region. The second doped region is on the first well region. The anode is coupled to the first doped region and the second well region. The cathode is coupled to the first well region and the second doped region. The first well region and the first doped region have a first conductivity type. The second well region and the second doped region have a second conductivity type opposite to the first conductivity type.

Abstract: An electrostatic discharge (ESD) protected device may include a substrate, an N-type well region disposed corresponding to a first portion of the substrate and having two N+ segments disposed at a surface thereof, an a P-type well region disposed proximate to a second portion of the substrate and having a P+ segment and an N+ segment. The two N+ segments may be spaced apart from each other and each may each be associated with an anode of the device. The N+ segment may be associated with a cathode of the device. A contact may be positioned in a space between the two N+ segments and connected to the P+ segment. The contact may form a parasitic capacitance that, in connection with a parasitic resistance formed in association with the N+ segment, provides self detection for high voltage ESD protection.

Abstract: A high voltage semiconductor element and an operating method thereof are provided. The high voltage semiconductor element comprises a high voltage metal-oxide-semiconductor transistor (HVMOS) and a NPN type electro-static discharge bipolar transistor (ESD BJT). The HVMOS has a drain and a source. The NPN type ESD BJT has a first collector and a first emitter. The first collector is electronically connected to the drain, and the first emitter is electronically connected to the source.

Abstract: An electrostatic discharge (ESD) protected device may include a substrate, an N+ doped buried layer, an N-type well region and a P-type well region. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may be disposed proximate to a portion of the N+ doped buried layer to form a collector region. The P-type well region may be disposed proximate to remaining portions of the N+ doped buried layer and having at least a P+ doped plate corresponding to a base region and distributed segments of N+ doped plates corresponding to an emitter region.

Abstract: A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region.

Abstract: Disclosed is a fluorescent coating and a method for making the same. At first, fluorescent powder is mixed with an anti-electrostatic solution. The mixture is cleared of impurities before it is dried and sintered. Thus, the fluorescent powder is coated with the anti-electrostatic material. The fluorescent powder coated with the anti-electrostatic material is plated on a side of a light-emitting diode (“LED”) chip by electrophoresis, thus forming a mixing zone on the side of the LED chip. Hence, the mixing zone is not vulnerable to deterioration or itiolation when it is subjected to heat in use. Accordingly, the life of the LED chip is long, and the illumination of the LED chip is high.

Abstract: A semiconductor structure is proposed. A third well is formed between a first well and a second well. A first doped region and a second doped region are formed in a surface of the third well. A third doped region is formed between the first doped region and the second doped region. A fourth doped region is formed in a surface of the first well. A fifth doped region is formed in a surface of the second well. A first base region and a second base region are respectively formed in surfaces of the first well and the second well. A first Schottky barrier is overlaid on a part of the first base region and the first doped region. A second Schottky barrier is overlaid on a part of the second base region and the second doped region.

Abstract: A semiconductor structure and a manufacturing method and an operating method for the same are provided. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, an anode, and a cathode. The second well region is adjacent to the first well region. The first doped region is on the second well region. The second doped region is on the first well region. The anode is coupled to the first doped region and the second well region. The cathode is coupled to the first well region and the second doped region. The first well region and the first doped region have a first conductivity type. The second well region and the second doped region have a second conductivity type opposite to the first conductivity type.