Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Abstract: A device for defibrillation and monitoring, a monitoring component, and a component for defibrillation and monitoring, are disclosed. The device for defibrillation and monitoring includes a host and a monitoring apparatus, which are assembled and disassembled through a detachably connection. The host is capable of independently performing defibrillation operations and display defibrillation information at least. Therefore, when it is necessary to go out for defibrillation operation alone, only the host is carried to medical assistance facilities. This monitoring apparatus can independently implement monitoring functions. When it is necessary to go out for implementing separate monitoring operations, just the monitoring apparatus is carried to the medical assistance facilities. Therefore, the user flexibly selects the devices they carry according to their requirements, improving the convenience of use.

Abstract: A back roller includes a roller body and a wear-resistant layer. The roller body has an axis and a roll surface disposed around the axis. The wear-resistant layer covers the roll surface. Vickers hardness (H) of the wear-resistant layer is 800 HV?H?1400 HV. The roll surface is covered by the wear-resistant layer, and the Vickers hardness (H) of the wear-resistant layer is controlled to be between 800 HV and 1400 HV, so that the roll surface is effectively protected, and wear resistance of the roll surface is improved. In this way, the wear-resistant layer is in direct contact with a material during operation, thereby effectively reducing an abrasion loss on the roll surface and extending the service life of the roll surface.

Abstract: An optical system may include a light source to provide a beam of light. The optical system may include a reflector to receive and redirect the beam of light. The optical system may include a light gate having an opening to permit the beam of light, from the reflector, to travel through the opening. The optical system may include a light sensor to receive a portion of the beam of light after the beam of light travels through the opening, and convert the portion of the beam of light to a signal. The optical system may include a processing device to determine whether a notch of a wafer is in an allowable position based on the signal.

Abstract: A curved prism array applied to an infrared sensor wherein: the infrared sensor comprises at least an infrared sensing element which is used in detecting infrared signals within a solid-angled FOV and installed inside the curved prism array; the curved prism array has an incident focal plane and a plurality of emergent focal planes, both of which are not parallel with each other, such that infrared signals beyond the solid-angled FOV are received by the incident focal plane, refracted through one of the emergent focal planes and guided toward the infrared sensing element for expansion of the solid-angled FOV of the infrared sensing element.

Abstract: The present disclosure belongs to the technical field of porous membrane material preparation, and specifically relates to a reverse osmosis composite membrane with an ultrathin desalting layer and a preparation method thereof; the intermediate layer is introduced after modifying the polysulfone base membrane, the modified polysulfone base membrane support layer may strengthen the bonding to the desalting layer through a covalent bond, and the thickness of the desalting layer is reduced to be ?10 nm, so that the desalination rate of the membrane is not greatly affected while increasing the membrane flux. Compared with the membrane having a conventional thickness of the desalting layer, the water flux of the reverse osmosis composite membrane with an ultrathin desalting layer may be increased by about 0.5 times, while the desalination rate has a small change.

Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.

Abstract: A touch control method is provided. The touch control method is applied in a touch device including a plurality of touch electrodes, the touch control method includes: step S1, sending a scanning signal to the plurality of touch electrodes, the scanning signal being a multi-frequency scanning signal; step S2, acquiring touch data according to the multi-frequency scanning signal; and step S3, calculating a current touch position according to the touch data.

Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.

Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first fin structure. The semiconductor device structure includes a first source/drain structure over the first fin structure. The semiconductor device structure includes a first dielectric layer over the first source/drain structure and the substrate. The semiconductor device structure includes a first conductive contact structure in the first dielectric layer and over the first source/drain structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive contact structure. The semiconductor device structure includes a first conductive via structure passing through the second dielectric layer and connected to the first conductive contact structure. A first width direction of the first conductive contact structure is substantially parallel to a second width direction of the first conductive via structure.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.

Abstract: Embodiments described herein provide systems and methods for training a sequential recommendation model. Methods include determining a difficulty and quality (DQ) score associated with user behavior sequences from a training dataset. User behavior sequences are sampled during training based on their DQ scores. A meta-extrapolator may also be trained based on user behavior sequences sampled according to DQ score. The meta-extrapolator may be trained with high quality low difficulty sequences. The meta-extrapolator may then be used with an input of high quality high difficulty sequences to generate synthetic user behavior sequences. The synthetic user behavior sequences may be used to augment the training dataset to fine-tune the sequential recommendation model, while continuing to sample user behavior sequences based on DQ score. As the DQ score is based on current model predictions, DQ scores iteratively update during the training process.

Abstract: The present disclosure relates to a semiconductor device with a hybrid fin-dielectric region. The semiconductor device includes a substrate, a source region and a drain region laterally separated by a hybrid fin-dielectric (HFD) region. A gate electrode is disposed above the HFD region and the HFD region includes a plurality of fins covered by a dielectric and separated from the source region and the drain region by the dielectric.

Abstract: A tamper-evident container including: a container body having a first hollow convex loop on a periphery of an opening thereof; and a lid having a second hollow convex loop and a force application structure, where the second hollow convex loop is used to engage with the first hollow convex loop, and a loop-shaped breakable line is provided on a loop-shaped top surface of the second hollow convex loop; where, when an illegitimate user applies a lifting force on any local area of the second hollow convex loop of the lid to make the local area moving upward with a displacement exceeding a threshold, a corresponding local area of the loop-shaped breakable line will be broken to show that the tamper-evident container has been tampered with.

Abstract: A self-moving robot and a method of automatically determining an accessible region are provided. The self-moving robot performs a setting process of 2D obstacles to generate a goal map based on an exploration map, performs a setting process of 3D obstacles on the goal map to update the accessible region of the goal map when a 3D obstacle is detected, performs an avoidance action, and, moves within the accessible region of the goal map. The disclosure prevents the self-moving robot from colliding with obstacles or being trapped.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises an insulating structure, a dielectric structure, a metal structure, a conductive spacer and a dielectric spacer. The dielectric structure is formed on the insulating structure. The metal structure is formed on and surrounded by the dielectric structure. A bottom surface and a lateral surface of the metal structure are in direct contact with the dielectric structure. The conductive spacer is formed on the insulating structure. The conductive spacer surrounds the dielectric structure. The dielectric spacer is formed on the insulating structure, wherein the dielectric spacer surrounds the conductive spacer.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments between the pair of source/drain regions; and a protection structure overlapping the gate electrode.