Patents by Inventor Huan Chen

Huan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11556065
    Abstract: A method includes moving a wafer stage to a first station on a table body of a lithography chamber; placing a wafer on a top surface of the wafer stage; emitting a first laser beam from a first laser emitter toward a first beam splitter on a first sidewall of the wafer stage, wherein a first portion of the first laser beam is reflected by the first beam splitter to form a first reflected laser beam, and a second portion of the first laser beam transmits through the first beam splitter to form a first transmitted laser beam; calculating a position of the wafer stage on a first axis based on the first reflected laser beam; after calculating the position of the wafer, moving the wafer stage to a second station on the table body; and performing a lithography process to the wafer.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: January 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Huan Chen, Yu-Chih Huang, Ya-An Peng, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20230010810
    Abstract: A system and a method for supplying target material in an EUV light source are provided. The system for supplying a target material comprises a priming assembly, a refill assembly and a droplet generator assembly. The priming is configured to transform the target material from a solid state to a liquid state. The refill assembly is in fluid communication with the priming assembly and configured to receive the target material in the liquid state from the priming assembly. Further, the refill assembly includes a purifier configured to purify the target material in the liquid state. The droplet generator assembly is configured to supply the target material in the liquid state from the refill assembly.
    Type: Application
    Filed: July 9, 2021
    Publication date: January 12, 2023
    Inventors: HSIN-FENG CHEN, MING-HSUN TSAI, LI-JUI CHEN, SHANG-CHIEH CHIEN, HENG-HSIN LIU, CHENG-HAO LAI, YU-HUAN CHEN, WEI-SHIN CHENG, YU-KUANG SUN, CHENG-HSUAN WU, YU-FA LO, CHIAO-HUA CHENG
  • Patent number: 11553581
    Abstract: A method for using an extreme ultraviolet radiation source is provided. The method includes assembling a first droplet generator onto a port of a vessel; ejecting a target droplet from the first droplet generator to a zone of excitation in front of a collector; emitting a laser toward the zone of excitation, such that the target droplet is heated by the laser to generate extreme ultraviolet (EUV) radiation; stopping the ejection of the target droplet; after stopping the ejection of the target droplet, disassembling the first droplet generator from the port of the vessel; after disassembling the first droplet generator from the port of the vessel, inserting a cleaning device into the vessel through the port; and cleaning the collector by using the cleaning device.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiao-Hua Cheng, Hsin-Feng Chen, Yu-Fa Lo, Yu-Kuang Sun, Wei-Shin Cheng, Yu-Huan Chen, Ming-Hsun Tsai, Cheng-Hao Lai, Cheng-Hsuan Wu, Shang-Chieh Chien, Heng-Hsin Liu, Li-Jui Chen, Sheng-Kang Yu
  • Patent number: 11537053
    Abstract: Some implementations herein include a detection circuit and a fast and accurate in-line method for detecting blockage on a droplet generator head of an extreme ultraviolet exposure tool without impacting the flow of droplets of a target material through the droplet generator head. In some implementations described herein, the detection circuit includes a switch circuit that is configured in an open configuration, in which the switch is electrically open between two electrode elements. When an accumulation of the target material occurs across two or more electrode elements on the droplet generator head, the accumulation functions as a switch that closes the detection circuit. A controller may detect closure of the detection circuit.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: December 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiao-Hua Cheng, Yu-Kuang Sun, Wei-Shin Cheng, Yu-Huan Chen, Ming-Hsun Tsai, Cheng-Hao Lai, Cheng-Hsuan Wu, Yu-Fa Lo, Shang-Chieh Chien, Heng-Hsin Liu, Li-Jui Chen, Sheng-Kang Yu
  • Patent number: 11533799
    Abstract: A system and a method for supplying target material in an EUV light source are provided. The system for supplying a target material comprises a priming assembly, a refill assembly and a droplet generator assembly. The priming is configured to transform the target material from a solid state to a liquid state. The refill assembly is in fluid communication with the priming assembly and configured to receive the target material in the liquid state from the priming assembly. Further, the refill assembly includes a purifier configured to purify the target material in the liquid state. The droplet generator assembly is configured to supply the target material in the liquid state from the refill assembly.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsin-Feng Chen, Ming-Hsun Tsai, Li-Jui Chen, Shang-Chieh Chien, Heng-Hsin Liu, Cheng-Hao Lai, Yu-Huan Chen, Wei-Shin Cheng, Yu-Kuang Sun, Cheng-Hsuan Wu, Yu-Fa Lo, Chiao-Hua Cheng
  • Patent number: 11528797
    Abstract: An extreme ultraviolet (EUV) photolithography system generates EUV light by irradiating droplets with a laser. The system includes a droplet generator with a nozzle and a piezoelectric structure coupled to the nozzle. The generator outputs groups of droplets. A control system applies a voltage waveform to the piezoelectric structure while the nozzle outputs the group of droplets. The waveform causes the droplets of the group to have a spread of velocities that results in the droplets coalescing into a single droplet prior to being irradiated by the laser.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Kuang Sun, Cheng-Hao Lai, Yu-Huan Chen, Wei-Shin Cheng, Ming-Hsun Tsai, Hsin-Feng Chen, Chiao-Hua Cheng, Cheng-Hsuan Wu, Yu-Fa Lo, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Patent number: 11527531
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
  • Patent number: 11521882
    Abstract: An optical system may include a light source to provide a beam of light. The optical system may include a reflector to receive and redirect the beam of light. The optical system may include a light gate having an opening to permit the beam of light, from the reflector, to travel through the opening. The optical system may include a light sensor to receive a portion of the beam of light after the beam of light travels through the opening, and convert the portion of the beam of light to a signal. The optical system may include a processing device to determine whether a notch of a wafer is in an allowable position based on the signal.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-An Chuang, Kuang-Wei Hsueh, Shih-Huan Chen, Yung-Shu Kao
  • Patent number: 11508845
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Liang Chu, Ta-Yuan Kung, Ker-Hsiao Huo, Yi-Huan Chen
  • Publication number: 20220367655
    Abstract: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei, Ming-Ta Lei, Ruey-Hsin Liu, Ta-Yuan Kung
  • Publication number: 20220367654
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Yi-Huan Chen, Kong-Beng Thei, Chien-Chih Chou, Alexander Kalnitsky, Szu-Hsien Liu, Huan-Chih Yuan
  • Publication number: 20220367709
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Inventors: YI-HUAN CHEN, CHIEN-CHIH CHOU, SZU-HSIEN LIU, KONG-BENG THEI, HUAN-CHIH YUAN, JHU-MIN SONG
  • Publication number: 20220367708
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments extending in parallel along the first direction; and a protection structure over the substrate and at least partially overlaps the gate electrode.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Inventors: YI-HUAN CHEN, CHIEN-CHIH CHOU, SZU-HSIEN LIU, KONG-BENG THEI
  • Publication number: 20220365442
    Abstract: Some implementations herein include a detection circuit and a fast and accurate in-line method for detecting blockage on a droplet generator head of an extreme ultraviolet exposure tool without impacting the flow of droplets of a target material through the droplet generator head. In some implementations described herein, the detection circuit includes a switch circuit that is configured in an open configuration, in which the switch is electrically open between two electrode elements. When an accumulation of the target material occurs across two or more electrode elements on the droplet generator head, the accumulation functions as a switch that closes the detection circuit. A controller may detect closure of the detection circuit.
    Type: Application
    Filed: October 6, 2021
    Publication date: November 17, 2022
    Inventors: Chiao-Hua CHENG, Yu-Kuang SUN, Wei-Shin CHENG, Yu-Huan CHEN, Ming-Hsun TSAI, Cheng-Hao LAI, Cheng-Hsuan WU, Yu-Fa LO, Shang-Chieh CHIEN, Heng-Hsin LIU, Li-Jui CHEN, Sheng-Kang YU
  • Publication number: 20220359502
    Abstract: A method of manufacturing a semiconductor device, including: forming a dielectric layer configured to be a gate oxide contacting the second well on the substrate, wherein the dielectric layer is single-layered dielectric layer and includes a contact via penetrating through the dielectric layer; and forming a patterned conductive layer contacting the dielectric layer, wherein the patterned conductive layer includes a first conductive portion isolated from the second well and configured to be a gate electrode, and a second conductive portion coupled to the first well via the contact via; wherein the first conductive portion is leveled with the second conductive portion, and the first conductive portion and the second conductive portion are formed entirely on a topmost surface of the dielectric layer; wherein the dielectric layer and the first conductive portion collectively serve as a gate of the transistor, and the transistor is configured as a high-voltage transistor.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: YI-SHENG CHEN, KONG-BENG THEI, FU-JIER FAN, JUNG-HUI KAO, YI-HUAN CHEN, KAU-CHU LIN
  • Patent number: 11494185
    Abstract: Techniques for managing threads involve acquiring respective runtime addresses and call information of a plurality of lock objects in a plurality of threads, and determining, from the plurality of lock objects, a first group of lock objects associated with first call information and a second group of lock objects associated with second call information different from the first call information. The techniques further involve providing an indication that a deadlock exists in the plurality of threads if it is determined that a first group of runtime addresses of the first group of lock objects overlaps with a second group of runtime addresses of the second group of lock objects. Accordingly, potential deadlocks in a plurality of threads can be analyzed, thereby avoiding the inability of the threads to proceed normally due to the deadlocks.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: November 8, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Ming Zhang, Huan Chen, Shuo Lv
  • Publication number: 20220352161
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 3, 2022
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei, Ming Chyi Liu, Shih-Chung Hsiao, Jhih-Bin Chen
  • Publication number: 20220350263
    Abstract: A method includes moving a wafer stage to a first station on a table body of a lithography chamber; placing a wafer on a top surface of the wafer stage; emitting a first laser beam from a first laser emitter toward a first beam splitter on a first sidewall of the wafer stage, wherein a first portion of the first laser beam is reflected by the first beam splitter to form a first reflected laser beam, and a second portion of the first laser beam transmits through the first beam splitter to form a first transmitted laser beam; calculating a position of the wafer stage on a first axis based on the first reflected laser beam; after calculating the position of the wafer, moving the wafer stage to a second station on the table body; and performing a lithography process to the wafer.
    Type: Application
    Filed: September 7, 2021
    Publication date: November 3, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Huan CHEN, Yu-Chih HUANG, Ya-An PENG, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
  • Publication number: 20220352152
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
  • Publication number: 20220338334
    Abstract: An extreme ultraviolet (EUV) photolithography system generates EUV light by irradiating droplets with a laser. The system includes a droplet generator with a nozzle and a piezoelectric structure coupled to the nozzle. The generator outputs groups of droplets. A control system applies a voltage waveform to the piezoelectric structure while the nozzle outputs the group of droplets. The waveform causes the droplets of the group to have a spread of velocities that results in the droplets coalescing into a single droplet prior to being irradiated by the laser.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 20, 2022
    Inventors: Yu-Kuang SUN, Cheng-Hao LAI, Yu-Huan CHEN, Wei-Shin CHENG, Ming-Hsun TSAI, Hsin-Feng CHEN, Chiao-Hua CHENG, Cheng-Hsuan WU, Yu-Fa LO, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU