Patents by Inventor Huan Chen

Huan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11855091
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei, Ming Chyi Liu, Shih-Chung Hsiao, Jhih-Bin Chen
  • Patent number: 11844633
    Abstract: A feature identifying method and an electronic device are provided. The method includes: obtaining a plurality of physiological information obtained by measuring a subject at a plurality of time points in one day; converting the plurality of physiological information into a plurality of correlation features respectively; establishing a plurality of first risk prediction models according to the plurality of correlation features, and identifying at least one first correlation feature from the plurality of correlation features according to the plurality of first risk prediction models; establishing a plurality of second risk prediction models according to the at least one first correlation feature, and identifying, according to the plurality of second risk prediction models, at least one second correlation feature capable of predicting a specific disease from the at least one first correlation feature; and outputting the at least one second correlation feature.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: December 19, 2023
    Assignees: Acer Incorporated, National Yang-Ming University
    Inventors: Chun-Hsien Li, Tsung-Hsien Tsai, Liang-Kung Chen, Chen-Huan Chen, Hao-Min Cheng
  • Patent number: 11841436
    Abstract: The present disclosure discloses a container positioning method and apparatus based on multi-line laser data fusion, the method comprising: acquiring point cloud data of at least two multi-line laser radars, and performing point cloud data fusion according to a coordinate system relationship between the at least two laser radars; performing clustering of scanning lines according to the fused point cloud data, and acquiring an edge point of a top surface or a side surface of a target container according to the clustered scanning lines; acquiring a contour of the top surface or the side surface of the target container according to the edge point of the top surface or the side surface of the target container to determine a central point and a heading angle of the target container so as to determine a position of the target container.
    Type: Grant
    Filed: September 12, 2021
    Date of Patent: December 12, 2023
    Assignee: Shanghai Master Matrix Information Technology Co., Ltd.
    Inventors: Zhi Feng, Hao Liang, Huan Chen
  • Publication number: 20230392923
    Abstract: A sensing module including an illumination device and a sensing device is disclosed. The illumination device is configured to provide an illumination beam or sequentially provide multiple sub-beams having directivity to a sensing area respectively, and the sensing area includes multiple different sub-sensing areas. The sensing device is configured to receive multiple reflected beams from the sub-sensing areas to respectively obtain multiple sub-depth signals, and generate a depth signal according to the sub-depth signals.
    Type: Application
    Filed: May 25, 2023
    Publication date: December 7, 2023
    Applicant: IGIANT OPTICS CO., LTD
    Inventors: Zih-Ying Fang, Jui-Hsiang Yen, Cheng-Huan Chen
  • Publication number: 20230377992
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 23, 2023
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Chia-Hong Wu
  • Patent number: 11823959
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Chia-Hong Wu
  • Publication number: 20230361188
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 9, 2023
    Inventors: Yi-Huan Chen, Kong-Beng Thei, Chien-Chih Chou, Alexander Kalnitsky, Szu-Hsien Liu, Huan-Chih Yuan
  • Publication number: 20230359133
    Abstract: A semiconductor substrate stage for carrying a substrate is provided. The semiconductor substrate stage includes a base layer, a magnetic shielding layer disposed on the base layer, a carrier layer disposed on the magnetic shielding layer, a receiver disposed on the carrier layer, a storage layer disposed between the base layer and the magnetic shielding layer, and a magnetic shielding element disposed on the carrier layer and surrounding the receiver.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 9, 2023
    Inventors: Yu-Huan CHEN, Yu-Chih HUANG, Ya-An PENG, Shang-Chieh CHIEN, Li-Jui CHEN, Heng-Hsin LIU
  • Patent number: 11810973
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments extending in parallel along the first direction; and a protection structure over the substrate and at least partially overlaps the gate electrode.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Szu-Hsien Liu, Kong-Beng Thei
  • Patent number: 11799007
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Kong-Beng Thei, Chien-Chih Chou, Alexander Kalnitsky, Szu-Hsien Liu, Huan-Chih Yuan
  • Publication number: 20230335411
    Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate including a substrate, a first pad, and a second pad. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the first pad is narrower than the second pad. The chip package structure includes a nickel layer over the first pad. The nickel layer has a T-shape in a cross-sectional view of the nickel layer. The chip package structure includes a chip over the wiring substrate. The chip package structure includes a conductive bump between the nickel layer and the chip.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Inventors: Kuo-Ching HSU, Yu-Huan CHEN, Chen-Shien CHEN
  • Publication number: 20230324554
    Abstract: The present disclosure discloses a container positioning method and apparatus based on multi-line laser data fusion, the method comprising: acquiring point cloud data of at least two multi-line laser radars, and performing point cloud data fusion according to a coordinate system relationship between the at least two laser radars; performing clustering of scanning lines according to the fused point cloud data, and acquiring an edge point of a top surface or a side surface of a target container according to the clustered scanning lines; acquiring a contour of the top surface or the side surface of the target container according to the edge point of the top surface or the side surface of the target container to determine a central point and a heading angle of the target container so as to determine a position of the target container.
    Type: Application
    Filed: September 12, 2021
    Publication date: October 12, 2023
    Applicant: Shanghai Master Matrix Information Technology Co., Ltd.
    Inventors: Zhi Feng, Hao Liang, Huan Chen
  • Patent number: 11782448
    Abstract: A method for obstacle detection and recognition for an intelligent snow sweeping robot is disclosed, comprising: 1) disposing ultrasonic sensors at a front end of the snow sweeping robot to detect distance information from an obstacle ahead; and disposing radar sensors at the front and rear of the snow sweeping robot to detect whether a creature suddenly approaches; 2) processing signals detected by each of the ultrasonic sensors and radar sensors, and calculating a forward distance of the snow sweeping robot; and 3) determining a snow cover extent of a working road, detecting a change of the distance from the obstacles, and recognizing the obstacles for conditions of an ultrasonic ranging variation ratio and a variation of the forward distance of the snow sweeping robot, a change of the signal detected by radar sensors, and a descriptive statistic of the snow cover extent within a specific time period.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: October 10, 2023
    Assignee: Chongqing University
    Inventors: Yongduan Song, Ziqiang Jiang, Shilei Tan, Junfeng Lai, Huan Liu, Li Huang, Jie Zhang, Huan Chen, Hong Long, Fang Hu, Jiangyu Wu, Qin Hu, Wenqi Li
  • Patent number: 11772264
    Abstract: The present disclosure discloses a neural network adaptive tracking control method for joint robots, which proposes two schemes: robust adaptive control and neural adaptive control, comprising the following steps: 1) establishing a joint robot system model; 2) establishing a state space expression and an error definition when taking into consideration both the drive failure and actuator saturation of the joint robot system; 3) designing a PID controller and updating algorithms of the joint robot system; and 4) using the designed PID controller and updating algorithms to realize the control of the trajectory motion of the joint robot. The present disclosure may solve the following technical problems at the same time: the drive saturation and coupling effect in the joint system, processing parameter uncertainty and non-parametric uncertainty, execution failure handling during the system operation, compensation for non-vanishing interference, and the like.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: October 3, 2023
    Assignee: Dibi (Chongqing) Intelligent Technology Research Institute Co., Ltd.
    Inventors: Yongduan Song, Huan Liu, Junfeng Lai, Ziqiang Jiang, Jie Zhang, Huan Chen, Li Huang, Congyi Zhang, Yingrui Chen, Yating Yang, Chunxu Ren, Han Bao, Kuilong Yang, Ge Song, Bowen Zhang, Hong Long
  • Publication number: 20230305643
    Abstract: A joystick module includes a casing, a movable component, a circuit board, a base, a swing arm, a joystick and a sensor. The movable component is disposed inside or outside the casing. The base is disposed within the casing. The swing arm is disposed within the casing, pivotally connected to the base and connected to the movable component for driving the movable component to move. The joystick is connected to the swing arm for driving the swing arm to move. The sensor is disposed on the circuit board and opposite to the movable component, and configured to sense a plurality of received signals from the movable component. The received signals are different with the movement of the movable component.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 28, 2023
    Inventors: Chun-Tseng HUNG, Hsin-Chang CHEN, Yi-Huan CHEN, Yi-Wei CHIU, Chih-Hsien CHUANG, Chi-Feng CHEN, Ying-Jui LEE
  • Publication number: 20230298702
    Abstract: Described herein are methods and assays for detection of recombination and/or rearrangement events in a cell. In some embodiments, the methods and/or assays relate to Linear Amplification Mediated (LAM)-PCR. In some embodiments, the recombination event is a V(D)J recombination event.
    Type: Application
    Filed: March 31, 2023
    Publication date: September 21, 2023
    Applicant: THE CHILDREN'S MEDICAL CENTER CORPORATION
    Inventors: Frederick W. ALT, Jiazhi HU, Sherry LIN, Zhou DU, Yu ZHANG, Huan CHEN
  • Patent number: 11748891
    Abstract: The present invention provides an automatic container loading and unloading apparatus and method. The apparatus comprises: a data acquisition module, used for scanning a container truck panel to obtain laser point cloud data; a data preprocessing module, used for segmenting a laser point cloud on a surface of the container truck panel from the laser point cloud data; a key point extraction module, used for performing edge extraction on the laser point cloud on the surface of the container truck panel to obtain discrete points on edges of the keel of the container truck panel; and a straight line fitting module, used for performing random sample consensus straight line fitting on the discrete points on the edges of the keel of the container truck panel to obtain spatial straight lines of the edges of the keel of the truck panel.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 5, 2023
    Assignee: Shanghai Master Matrix Information Technology Co., Ltd.
    Inventors: Junming Hong, Huan Chen
  • Patent number: 11747741
    Abstract: A semiconductor substrate stage for carrying a substrate is provided. The semiconductor substrate stage includes a base layer, a magnetic shielding layer disposed on the base layer, a carrier layer disposed on the magnetic shielding layer, and a receiver disposed on the carrier layer. The receiver is configured to receive a microwave signal from a signal source electrically isolated from the receiver, and the microwave signal is used for controlling the movement of the semiconductor substrate stage.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Huan Chen, Yu-Chih Huang, Ya-An Peng, Shang-Chieh Chien, Li-Jui Chen, Heng-Hsin Liu
  • Publication number: 20230268435
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer and contacting the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Inventors: YI-HUAN CHEN, CHIEN-CHIH CHOU, SZU-HSIEN LIU, KONG-BENG THEI, HUAN-CHIH YUAN, JHU-MIN SONG
  • Publication number: 20230260994
    Abstract: Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Inventors: Yu-Chang Jong, Yi-Huan Chen, Chien-Chih Chou, Tsung-Chieh Tsai, Szu-Hsien Liu, Huan-Chih Yuan, Jhu-Min Song