Abstract: The present application discloses a semiconductor device including a substrate, an active area in the substrate, a first plug positioned above the active area, second plugs positioned above the active area, metal spacers positioned above the first plug and the plurality of second plugs, and air gaps respectively positioned between the plurality of metal spacers. The active area includes a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view.

Abstract: Provided herein are antibodies that bind to the alpha subunit of an IL-7 receptor (IL-7R?). Also provided are uses of these antibodies in therapeutic applications, such as treatment of inflammatory diseases. Further provided are cells that produce the antibodies, polynucleotides encoding the heavy and/or light chain regions of the antibodies, and vectors comprising the polynucleotides.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first semiconductor die comprising a first capacitor, and a second semiconductor die in contact with the first semiconductor die and comprises a diode. The first semiconductor die and the second semiconductor die are arranged along a first direction, and a diode is configured to direct electrons accumulated at the first capacitor to a ground.

Abstract: Described herein are systems and methods for extracting borderless checkbox tables from electronic documents. A server detects checkboxes in a textual electronic document. The server extracts text blocks from the textual electronic document. The server identifies table headers corresponding to a borderless checkbox table in the textual electronic document based on the text blocks. The server determines a table boundary corresponding to the borderless checkbox table based on the table headers. The server identifies table rows and table columns corresponding to the borderless checkbox table based on the table boundary and the checkboxes. The server identifies table cells corresponding to the borderless checkbox table based on the table rows and the table columns. The server generates a data structure comprising data representing the borderless checkbox table based on at least the table cells and the checkboxes.

Abstract: The present disclosure provides a packing method including following steps. Genetic algorithm is utilized to calculate multiple packing programs. Multiple candidate packing programs including all items are selected from the packing programs. Among each of the candidate packing programs, at least one of the items to be placed earlier is classified into a first subset, and at least another one of the items to be placed later is classified into a second subset. Among each of the candidate packing programs, a first packing for the first subset is maintained, and a second packing for the second subset is recalculated by using a greedy algorithm to generate an updated second packing.

Abstract: An inertia braking test system and a control method is provided, wherein the inertia braking test system is composed of an inertia brake test system, a sensor system and a tested object. An actuating device is connected with the inertia brake control device through a ball stud. The actuation function of the inertia brake control device with two degrees of freedom along the front-and-rear direction and the up-and-down direction of the vehicle is realized. The movable chassis realizes the mobile function of the system. The acceleration sensor can sense the acceleration of the movable chassis. Each force is tested by the first force sensor, the second force sensor and the third force sensor. The displacement data is measured by the first displacement sensor and the second displacement sensor, so that a movable brake system test is achieved.

Abstract: A cantilever probe card device and a focusing probe thereof are provided. The focusing probe includes a soldering segment, a testing segment, two outer elastic arms spaced apart from each other, and a focusing portion. The testing segment is spaced apart from the soldering segment along an arrangement direction, and has a needle tip, an outer edge, and an inner edge that is opposite to the outer edge. Each of the two outer elastic arms has two end portions respectively connected to the soldering segment and the inner edge of the testing segment. The focusing portion is connected to the inner edge and is located between the needle tip and the two outer elastic arms, and has a plurality of focusing points arranged on one side thereof away from the two outer elastic arms.

Abstract: Fin and nanostructured channel structure formation techniques for three-dimensional transistors can tune device performance. For example, fin profile control can be achieved by modifying the shape of fins/nanostructured channel structures so as to reduce their line edge roughness. Consequently, current flow within the channel regions of fins and nanostructured channel structures can be improved, enhancing device performance.

Abstract: Various embodiments of the present disclosure provide a semiconductor device structure.

Abstract: The present disclosure provides a semiconductor device, including a first semiconductor structure and a second semiconductor structure. Each of the first semiconductor structure and the second semiconductor structure includes a substrate; a through silicon via, penetrating the substrate; and a deep trench capacitor, disposed in the substrate, separated from the TSV by a distance. The deep trench capacitor includes a stack, including a dielectric layer between a pair of conductive layers in a trench; and an insulating layer, covering the stack and the trench. The insulating layer surround a plurality of voids in the trench.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a plurality of conductive contacts overlying a semiconductor substrate. A plurality of first conductive wires is disposed on the plurality of conductive contacts. A plurality of conductive vias overlies the first conductive wires. An etch stop structure is disposed on the first conductive wires. The plurality of conductive vias extend through the etch stop structure. The etch stop structure includes a first etch stop layer, a first insulator layer, and a second etch stop layer. The first insulator layer is disposed between the first etch stop layer and the second etch stop layer.

Abstract: Various embodiments of the present application are directed towards an integrated chip (IC). The IC comprises a trench capacitor overlying a substrate. The trench capacitor comprises a plurality of capacitor electrode structures, a plurality of warping reduction structures, and a plurality of capacitor dielectric structures. The plurality of capacitor electrode structures, the plurality of warping reduction structures, and the plurality of capacitor dielectric structures are alternatingly stacked and define a trench segment that extends vertically into the substrate. The plurality of capacitor electrode structures comprise a metal component and a nitrogen component. The plurality of warping reduction structures comprise the metal component, the nitrogen component, and an oxygen component.

Abstract: Systems and methods for extracting data from electronic documents using optical character recognition (OCR) and non-OCR based text extraction. A server computing device initiates non-OCR based text extraction for each page of an electronic document. The server calculates a document text coverage percentage corresponding to the non-OCR based text extraction for the whole document and, in response to determining that the document text coverage percentage is below a first threshold, initiates OCR for the document. The server calculates a page text coverage percentage corresponding to the non-OCR based text extraction for one or more pages of the electronic document and, in response to determining that the page text coverage percentage is below a second threshold, initiates OCR for the pages. The server combines first text extracted from the electronic document using non-OCR based text extraction and second text extracted from the electronic document using OCR.

Abstract: The present application discloses a semiconductor device including a substrate, an active area in the substrate, a first plug positioned above the active area, second plugs positioned above the active area, metal spacers positioned above the first plug and the plurality of second plugs, and air gaps respectively positioned between the plurality of metal spacers. The active area includes a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view.

Abstract: The present disclosure provides a method for preparing a semiconductor device structure with a fluorine-catching layer. The method includes forming a first dielectric layer over a semiconductor substrate, and forming a first conductive via structure in the first dielectric layer. The method also includes forming a second dielectric layer over the first dielectric layer and covering the first conductive via structure, and forming a fluorine-catching layer over the second dielectric layer. The method further includes forming a third dielectric layer over the fluorine-catching layer, and forming a second conductive via structure in the third dielectric layer, the fluorine-catching layer, and the second dielectric layer.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.

Abstract: The present disclosure provides a semiconductor device structure with a fluorine-catching layer. The semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a fluorine-catching layer disposed over the second dielectric layer, and a third dielectric layer disposed over the fluorine-catching layer. The semiconductor device structure further includes a conductive via structure penetrating through the third dielectric layer, the fluorine-catching layer, and the second dielectric layer to contact the first dielectric layer.