Abstract: The present subject matter relates to backlight keyboards. In an example implementation of the present subject matter, backlight keyboards and methods of fabricating lighting units for such backlight keyboards are described. In an example, a backlight keyboard includes a substrate and a plurality of Light Emitting Diodes (LEDs) disposed on the substrate. The backlight keyboard further includes a printed circuit disposed on the substrate, where the printed circuit comprises of a plurality of electrical connections to provide electric current to the plurality of LEDs, and where width of each of the plurality of electrical connections is predefined to control brightness of a corresponding LED from amongst the plurality of LEDs.

Abstract: In one example, a metal-plastic composite structure for an electronic device is described, which includes a micro-arc oxidized metal substrate and at least one plastic film disposed on the micro-arc oxidized metal substrate using a superplastic forming process.

Abstract: The present subject matter relates to self-healing touch-surface components. In an example implementation, a self-healing touch-surface component of an electronic device comprises a self-healing layer disposed over a touch-surface component. The self-healing layer includes polyurethane, polyester, epoxy, polyurethane microcapsules filled with di-n-butyltin dilaurate, and a polysiloxane mixture.

Abstract: A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.

Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

Abstract: A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. An upper portion of the fin structure includes a first surface and a second surface which is inclined to the first surface. The semiconductor device structure also includes an isolation feature surrounding a lower portion of the fin structure. The semiconductor device structure further includes a passivation layer covering the first surface and the second surface of the upper portion. The passivation layer includes a semiconductor material and has a substantially uniform thickness. In addition, the semiconductor device structure includes an interfacial layer over the passivation layer. The interfacial layer includes the semiconductor material. The interfacial layer has a first portion covering the fin structure and a second portion covering the isolation feature.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A fin field effect transistor (FinFET) including a first insulation region and a second insulation region and fin there between. A gate stack is disposed over a first portion of the fin. A strained source/drain material is disposed over a second portion of the fin. The strained source/drain material has a flat top surface extending over the first and second insulation regions. The first insulation region may include a tapered top surface.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. An upper portion of the fin structure includes a first surface and a second surface which is inclined to the first surface. The semiconductor device structure also includes an isolation feature surrounding a lower portion of the fin structure. The semiconductor device structure further includes a passivation layer covering the first surface and the second surface of the upper portion. The passivation layer includes a semiconductor material and has a substantially uniform thickness. In addition, the semiconductor device structure includes an interfacial layer over the passivation layer. The interfacial layer includes the semiconductor material. The interfacial layer has a first portion covering the fin structure and a second portion covering the isolation feature.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The fin structure includes a first surface and a second surface. The first surface is inclined to the second surface. The semiconductor device structure also includes a passivation layer covering the first surface and the second surface of the fin structure. The thickness of a first portion of the passivation layer covering the first surface is substantially the same as that of a second portion of the passivation layer covering the second surface.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at least a bottom surface of the void being defined by the one of the two insulation regions. The integrated circuit structure further includes a first semiconductor strip between and adjoining the two insulation regions, where the first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions, a gate dielectric over a top surface and sidewalls of the fin, and a gate electrode over the gate dielectric.

Abstract: An exemplary method of forming a fin field effect transistor that includes first and second etching processes to form a fin structure. The fin structure includes an upper portion and a lower portion separated at a transition. The upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The fin structure includes a first surface and a second surface. The first surface is inclined to the second surface. The semiconductor device structure also includes a passivation layer covering the first surface and the second surface of the fin structure. The thickness of a first portion of the passivation layer covering the first surface is substantially the same as that of a second portion of the passivation layer covering the second surface.

Abstract: A fin field effect transistor (FinFET) including a first insulation region and a second insulation region and fin there between. A gate stack is disposed over a first portion of the fin. A strained source/drain material is disposed over a second portion of the fin. The strained source/drain material has a flat top surface extending over the first and second insulation regions. The first insulation region may include a tapered top surface.

Abstract: A mediator-type photocell system is provided. The mediator-type photocell system includes a galvanic cell having a galvanic cell anode and a galvanic cell cathode; and a light capturing portion, including a light capturing cathode corresponding to the galvanic cell anode; and a light capturing anode electrically connected to the light capturing cathode via a conductive element, and corresponding to the galvanic cell cathode, wherein the galvanic cell cathode and the light capturing anode have a first mediator therebetween, the galvanic cell anode and the light capturing cathode have a second mediator therebetween, an oxide is generated to be provided to the galvanic cell cathode when the first mediator is illuminated, and a reducing substance is generated to be provided to the galvanic cell anode when the second mediator is illuminated.

Abstract: A pivot mechanism rotatably coupes a cover to a base of a foldable electronic device. The pivot mechanism includes a connector, a first rotation assembly, and a second rotation assembly. The first rotation assembly is rotatably coupled to the base and fixedly attached to the connector. The second rotation assembly is fixedly coupled to the cover and rotatably coupled to the connector. The first rotation assembly rotates relative to the base and the second rotation assembly remains fixed relative to the connector as the cover is rotated open to a first angle. The second rotation assembly rotates relative to the connector as the cover is rotated further to a second angle.