Abstract: A computer system includes a processor that operates in a normal world and a secure world and that provides hardware-level isolation between the normal world and the secure world. A storage device of the computer system has a protected data region that stores critical data. A random-access memory of the computer system has a normal memory space that is accessible in the normal world and a secure memory space that is accessible only in the secure world. The secure memory space stores commands that transfer the critical data between the protected data region and the normal memory space by direct memory access.

Abstract: An apparatus including a control unit, a memory having computer program code, and N groups of storage units electrically connected to the control unit is disclosed. Each of the N groups of storage units has N storage units, each of the N storage units has N storage regions, wherein N is a positive integer. The memory and the computer program code configured to, with the control unit, cause the apparatus to perform: storing a first data segment into an ith storage region of a first storage unit of a kth group of storage units; storing a fourth data segment into an ith storage region of a first storage it of a (k+1)th group of storage units; storing a fifth data segment into an ith storage region of a second storage unit of the (k+1)th group of storage units; and storing a sixth data segment into an ith storage region of a third storage unit of the (k+1)th group of storage units.

Abstract: An apparatus including a control unit, a memory having computer program code, and N groups of storage units electrically connected to the control unit is disclosed. Each of the N groups of storage units has N storage units, each of the N storage units has N storage regions, wherein N is a positive integer The memory and the computer program code configured to, with the control unit, cause the apparatus to perform: storing a first data segment into an ith storage region of a first storage unit of a kth group of storage units; storing a fourth data segment into an ith storage region of a first storage it of a (k+1)th group of storage units; storing a fifth data segment into an storage region of a second storage unit of the (k+1)th group of storage units; and storing a sixth data segment into an ith storage region of a third storage unit of the (k+1)th group of storage units.

Abstract: An apparatus includes a control unit, a memory having computer program code, and a first storage unit. The first storage unit comprises a first consecutive storage region and a second consecutive storage region. The first storage unit stores a number M of categories of first data having a first attribute in the first consecutive storage region and a number N of first error correction data in the second consecutive storage region. The number N of first error correction data stored in the second consecutive storage region of the first storage unit are independent of the number M of categories of first data stored in the first consecutive storage region of the first storage unit.

Abstract: In some aspects, the disclosure is directed to methods and systems for utilizing a thin-film bulk acoustic resonator (FBAR) as a frequency reference for a phase-locked loop (PLL) circuit controlling frequency of a voltage controlled oscillator (VCO). In some implementations, the FBAR-based oscillator may be used as a reference to an analog or digital PLL circuit (either directly, or divided to a lower frequency). In other implementations, the FBAR-based oscillator may be used as a reference to a mixing-based PLL rather than a dividing-based PLL. Through these implementations, the noise contribution of many of the PLL circuit components or elements may be reduced (e.g. noise from a delta-sigma modulator (DSM), multiple modulus divider (MMD), phase frequency detector (PFD)/charge pump (CP), etc.).

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: A synchronous switching regulator circuit for supply regulation of a switching circuit includes a pass transistor to couple the switching circuit to a supply voltage. The synchronous switching regulator circuit further includes a switch that is operable to synchronously turn off a flow of a supply current through the pass transistor. The switching circuit can be controlled by a switching signal, and the switch can operate in synchronization with the switching circuit.

Abstract: A synchronous switching regulator circuit for supply regulation of a switching circuit includes a pass transistor to couple the switching circuit to a supply voltage. The synchronous switching regulator circuit further includes a switch that is operable to synchronously turn off a flow of a supply current through the pass transistor. The switching circuit can be controlled by a switching signal, and the switch can operate in synchronization with the switching circuit.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: A transmitter capable of operating according to a first standard that does not interfere with a nearby frequency generator operating according to a second standard. The transmitter comprises an oscillator, a frequency divider, a mixer, and a filter. The oscillator is configured to output a first frequency that is outside of a frequency harmonic of the frequency generator. The frequency divider is coupled to the oscillator and divides the first frequency by a selective divide ratio to produce a second frequency. The mixer is configured to receive the first and second frequencies, which combines them to produce a mixed frequency. The filter is then used to filters the mixed frequency to obtain the higher portion of the mixed frequency. The divide ratio of the frequency divider is selected base on the desired output frequency of the transmitter such that a 2.4 GHz or 5 GHz ISM band frequency is achieved.

Abstract: The invention discloses a data storage unit and a redundant data storage system including such data storage unit. The data storage unit of the invention includes an internal storage area network (SAN) switch module, a storage server module and a storage device. The internal SAN switch module includes a first external transmission interface and a first internal transmission interface. The storage server module includes a second external transmission interface and a second internal transmission interface. The storage server module is respectively connected to the storage device and the first internal transmission interface through the second internal transmission interface. The internal SAN switch module is connected to the storage device through the first internal transmission interface.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: The invention discloses a data storage unit and a redundant data storage system including such data storage unit. The data storage unit of the invention includes an internal storage area network (SAN) switch module, a storage server module and a storage device. The internal SAN switch module includes a first external transmission interface and a first internal transmission interface. The storage server module includes a second external transmission interface and a second internal transmission interface. The storage server module is respectively connected to the storage device and the first internal transmission interface through the second internal transmission interface. The internal SAN switch module is connected to the storage device through the first internal transmission interface.

Abstract: A cloud data storage system is provided for multiple clients to access data of files comprising at least one node connecting to a first storage means; at least one namenode module for processing file operations issued from the clients, namenode module issuing data access instructions to access and maintain the metadata on the first storage means; at least one datanode module respectively executing on at least one node, each datanode module functioning to scan and access a second storage means connected thereto; at least one data import module selectively executing on nodes in which datanode module are executing, the data import module scanning a second storage means newly connected to the cloud data storage system and obtaining a corresponding metadata, and executing data migration operation for the data in second storage means without actual physical uploading operation.

Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.

Abstract: The invention discloses a data storage system and managing method thereof. The data storage system according to the invention includes N storage devices, a backup memory and a controller where N is a natural number. Each storage device has a respective write cache. Once the data storage system suffers from power failure, the backup memory still reserves data stored therein. The controller receives data transmitted from an application I/O request unit, executes a predetermined operation for the received data to generate data to be written, transmits the data to be written to the write caches of the storage devices, duplicates the data to be written into the backup memory, and labels the duplicated data in the backup memory as being valid in response to a writing confirm message sent from the storage devices.

Abstract: Aspects of a method and system for processing signals in a high performance receive chain may include amplifying a plurality of radio frequency signals in one or more respective one or ones of a plurality of amplifier chains in a multistandard radio frequency front-end, which may comprise one or more shared processing stages. The plurality of radio frequency signals may be compliant with a plurality of radio frequency communication standards and may be received concurrently. The one or more shared processing stages may be shared between two or more of the plurality of amplifier chains. Each of the two or more of the plurality of amplifier chains may be operable to amplify signals compliant with different radio frequency communication standards.

Abstract: Certain aspects of a method and system for mitigating effects of pulling in multiple phase locked loops in multi-standard systems may include selecting an input frequency range of operation at a voltage controlled oscillator based on a particular wireless band of operation in a system that handles a first wireless communication protocol and a second wireless communication protocol. An image rejection mixer may be enabled to generate an output signal for the particular wireless band of operation based on mixing a plurality of received signals within a selected frequency range. An in-phase (I) component and a quadrature (Q) component of the generated output signal may be generated by utilizing a RC-CR quadrature network.