Patents by Inventor Hung-Yi Huang
Hung-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240150568Abstract: The invention provides a high thermal conductivity fluororesin composition and products thereof. The high thermal conductivity fluororesin composition includes a polytetrafluoroethylene resin, a fluorine-containing copolymer, spherical inorganic fillers and impregnation aids.Type: ApplicationFiled: March 16, 2023Publication date: May 9, 2024Inventors: Te-Chao Liao, Hung-Yi Chang, Chia-Lin Liu, Wei-Ru Huang
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Publication number: 20240150547Abstract: A composite material substrate includes an inorganic filler, a resin composition, and a dispersant. The resin composition includes a bismaleimide resin, a naphthalene ring-containing epoxy resin, and a benzoxazine resin. The inorganic filler, the resin composition, and the dispersant are mixed together.Type: ApplicationFiled: November 23, 2022Publication date: May 9, 2024Applicant: NAN YA PLASTICS CORPORATIONInventors: Te-Chao Liao, Hung-Yi Chang, Chia-Lin Liu, Wei-Ru Huang
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Publication number: 20240130686Abstract: A coupled physiological signal measuring device is provided. The coupled physiological signal measuring device includes at least two measuring electrodes, a signal processing unit and a multiplex feedback circuit unit. The measuring electrodes are used to obtain a real-time physiological signal through measurement. The signal processing unit includes a discharge control element. If an electrostatic surge of the real-time physiological signal meets a condition, a discharge control signal is outputted. The multiplex feedback circuit unit is used to discharge the measuring electrodes according to the discharge control signal.Type: ApplicationFiled: January 20, 2023Publication date: April 25, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yun-Yi HUANG, Yu-Chiao TSAI, Hung-Hsien KO, Heng-Yin CHEN
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Patent number: 11956583Abstract: Disclosed is a headphone including a headband and two ear cups connected to opposite ends of the headband. Each of the ear cups includes a shell, a front cover, and a light sensor. The shell has an open end. The front cover covers the open end of the shell. The front cover is in a basin form and has a peripheral sidewall and a bottom wall. The light sensor is located on the peripheral sidewall of the front cover. The light sensor includes a light-emitting unit and a light detection unit. When a user wears the headphone, light emitted by the light-emitting unit irradiates a flat portion of a back surface of an ear of the user.Type: GrantFiled: April 22, 2022Date of Patent: April 9, 2024Assignee: Merry Electronics Co., Ltd.Inventors: Hung-Uei Jou, Ko-Min Wang, Chung-Yi Huang
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Publication number: 20240105550Abstract: A device includes an integrated circuit die attached to a substrate; a lid attached to the integrated circuit die; a sealant on the lid; a spacer structure attached to the substrate adjacent the integrated circuit die; and a cooling cover attached to the spacer structure, wherein the cooling cover extends over the lid, wherein the cooling cover attached to the lid by the sealant. In an embodiment, the device includes a ring structure on the substrate, wherein the ring structure is between the spacer structure and the integrated circuit die.Type: ApplicationFiled: January 10, 2023Publication date: March 28, 2024Inventors: Tung-Liang Shao, Yu-Sheng Huang, Hung-Yi Kuo, Chen-Hua Yu
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Patent number: 11901183Abstract: A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.Type: GrantFiled: August 9, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Hsiu Hung, Chien Chang, Yi-Hsiang Chao, Hung-Yi Huang, Chih-Wei Chang
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Patent number: 11853120Abstract: A foldable terminal and a screen-on control method for the foldable terminal, where the foldable terminal includes a body, a display component, a processor, and a covering detection sensor. The body includes a first body part and a second body part that are connected in a foldable connection manner, the display component includes two display parts. The covering detection sensor is configured to detect whether the first body part is covered with a terminal protective case. The processor is configured to control a to-be-used display part to be completely or partially on when the covering detection sensor detects that the first body part is not covered with the terminal protective case.Type: GrantFiled: August 19, 2020Date of Patent: December 26, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Qinghao Jin, Hung-Yi Huang
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Publication number: 20230402366Abstract: A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.Type: ApplicationFiled: June 9, 2022Publication date: December 14, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Hsu-Kai CHANG, Kuan-Kan HU, Ken-Yu CHANG, Hung-Yi HUANG, Harry CHIEN, Wei-Yip LOH, Chun-I TSAI, Hong-Mao LEE, Sung-Li WANG, Pinyen LIN, Chuan-Hui SHEN
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Publication number: 20230395504Abstract: Provided are devices with conductive contacts and methods for forming such devices. A method includes forming a lower conductive contact in a dielectric material and over a structure, wherein the lower conductive contact has opposite sidewalls that extend to and terminate at a top surface. The method also includes separating an upper portion of each sidewall from the dielectric material and locating a barrier material between the upper portion of each sidewall and the dielectric material. Further, the method includes forming an upper conductive contact over the lower conductive contact.Type: ApplicationFiled: June 1, 2022Publication date: December 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu Pei Chen, Chia-Hao Chang, Shin-Yi Yang, Chia-Hung Chu, Po-Chin Chang, Shuen-Shin Liang, Chun-Hung Liao, Yuting Cheng, Hung-Yi Huang, Harry Chien, Pinyen Lin, Sung-Li Wang
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Publication number: 20230395429Abstract: Depositing a seed layer after formation of the MD in order to reduce or prevent epitaxial growth of the seed layer toward the MD. For example, the seed layer may be deposited using CVD and conformal dry etching. In some implementations, the seed layer may be formed of ruthenium (Ru), molybdenum (Mo), or tungsten (W). Accordingly, the seed layer helps reduce or prevent seam formation in the VG, which reduces resistance of the VG by allowing for bottom-up metal growth. Additionally, current leakage from the VG to the MD is reduced or even prevented. As a result, device performance and efficiency are increased and breakdown voltage of the gate structure is also increased. Additionally, because electrical shorts are less likely, yield is increased, which conserves power, raw materials, and processing resources that otherwise would have been consumed during manufacture.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Inventors: Kan-Ju LIN, Hao-Heng LIU, Chien CHANG, Hung-Yi HUANG, Harry CHIEN
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Patent number: 11817384Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.Type: GrantFiled: January 3, 2022Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shuen-Shin Liang, Ken-Yu Chang, Hung-Yi Huang, Chien Chang, Chi-Hung Chuang, Kai-Yi Chu, Chun-I Tsai, Chun-Hsien Huang, Chih-Wei Chang, Hsu-Kai Chang, Chia-Hung Chu, Keng-Chu Lin, Sung-Li Wang
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Publication number: 20230299168Abstract: A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.Type: ApplicationFiled: March 15, 2022Publication date: September 21, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuan-Kan HU, Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Hsu-Kai CHANG, Ken-Yu CHANG, Wei-Yip LOH, Hung-Yi HUANG, Harry CHIEN, Sung-Li WANG, Pinyen LIN, Chuan-Hui SHEN, Tzu-Pei CHEN, Yuting CHENG
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Publication number: 20230260847Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.Type: ApplicationFiled: April 28, 2023Publication date: August 17, 2023Inventors: Wei-Yip LOH, Yan-Ming TSAI, Yi-Ning TAI, Raghunath PUTIKAM, Hung-Yi HUANG, Hung-Hsu CHEN, Chih-Wei CHANG
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Publication number: 20230253308Abstract: A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.Type: ApplicationFiled: February 10, 2022Publication date: August 10, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hung CHU, Po-Chin CHANG, Tzu-Pei CHEN, Yuting CHENG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Pinyen LIN, Sung-Li WANG, Sheng-Tsung WANG, Lin-Yu HUANG, Shao-An WANG, Harry CHIEN
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Publication number: 20230230916Abstract: A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.Type: ApplicationFiled: January 18, 2022Publication date: July 20, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Tzu-Pei CHEN, Ken-Yu CHANG, Hung-Yi HUANG, Harry CHIEN, Wei-Yip LOH, Chun-I TSAI, Hong-Mao LEE, Sung-Li WANG, Pinyen LIN
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Publication number: 20230185334Abstract: This application provides an electronic device. The electronic device includes a foldable display, a folding rotating shaft, and at least one camera. The display includes a first display subarea and a second display subarea. The folding rotating shaft is configured to fold or unfold the first display subarea and the second display subarea. The at least one camera is disposed on the rear of the first display subarea. When the first display subarea and the second display subarea are in a folded state, the rear of the first display subarea is opposite to the rear of the second display subarea, and the at least one camera is used as a front-facing camera in the second display subarea. Therefore, the electronic device in the embodiments of this application can support a selfie function, and may also have a relatively high screen-to-body ratio.Type: ApplicationFiled: October 13, 2022Publication date: June 15, 2023Inventors: Yuelong Liao, Hung-Yi Huang, Qinghao Jin, Lupeng Yao
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Patent number: 11676868Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.Type: GrantFiled: August 19, 2021Date of Patent: June 13, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yip Loh, Yan-Ming Tsai, Yi-Ning Tai, Raghunath Putikam, Hung-Yi Huang, Hung-Hsu Chen, Chih-Wei Chang
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Publication number: 20230137108Abstract: Techniques described herein include performing a first anneal operation on a first portion of the interconnect, filling the remaining portion of the interconnect, and then performing a second anneal operation on the interconnect. The two-step anneal techniques described herein enable the removal of defects in an interconnect structure, particularly for high aspect ratio interconnect structures. Accordingly, the two-step anneal techniques described herein may be used to fabricate defect free or near defect free interconnect structures in a semiconductor device. This reduces contact resistance for the interconnect structures, reduces premature device failure for the semiconductor device, increases manufacturing yield, and increases tolerance of the interconnect structures to subsequent processing operations, among other examples.Type: ApplicationFiled: January 6, 2022Publication date: May 4, 2023Inventors: Kan-Ju LIN, Chien CHANG, Chih-Shiun CHOU, Tai Min CHANG, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI, Lin-Yu HUANG
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Publication number: 20230095976Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.Type: ApplicationFiled: December 5, 2022Publication date: March 30, 2023Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
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Patent number: D1012127Type: GrantFiled: September 29, 2020Date of Patent: January 23, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Lingsong Jin, Hung-yi Huang, Bin Xie