Patents by Inventor Husam N. Al-Shareef
Husam N. Al-Shareef has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7410911Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° C. to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.Type: GrantFiled: October 17, 2005Date of Patent: August 12, 2008Assignee: Micron Technology, Inc.Inventors: Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
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Patent number: 7282457Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace is disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmosphere to 25 atmosphere N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.Type: GrantFiled: March 2, 2001Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventors: Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
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Patent number: 7279435Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five (5) atmospheres to twenty-five (25) atmospheres N2O and a temperature range of 600° C. to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.Type: GrantFiled: September 2, 2004Date of Patent: October 9, 2007Assignee: Micron Technology, Inc.Inventors: Daniel F. Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
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Patent number: 7206215Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film. Embodiments include a method of operating an antifuse, comprising applying a voltage across electrodes of a capacitor having a tantalum oxynitride film and forming a hole in the tantalum oxynitride film.Type: GrantFiled: August 29, 2002Date of Patent: April 17, 2007Assignee: Micron Technology, Inc.Inventors: Scott Jeffrey DeBoer, Husam N. Al-Shareef, Randhir P. S. Thakur, Dan Gealy
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Patent number: 7176079Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.Type: GrantFiled: July 26, 2001Date of Patent: February 13, 2007Assignee: Micron Technology, Inc.Inventors: Ronald A. Weimer, Scott J. DeBoer, Dan Gealy, Husam N. Al-Shareef
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Patent number: 7064052Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.Type: GrantFiled: April 29, 2002Date of Patent: June 20, 2006Assignee: Micron Technology, Inc.Inventors: Ronald A. Weimer, Scott J. DeBoer, Dan Gealy, Husam N. Al-Shareef
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Patent number: 7038265Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.Type: GrantFiled: March 7, 2005Date of Patent: May 2, 2006Assignee: Micron Technology, Inc.Inventors: Scott Jeffrey DeBoer, Husam N. Al-Shareef, Randhir P. S. Thakur, Dan Gealy
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Patent number: 7022623Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.Type: GrantFiled: April 22, 1999Date of Patent: April 4, 2006Assignee: Micron Technology, Inc.Inventors: Ronald A. Weimer, Scott J. DeBoer, Dan Gealy, Husam N. Al-Shareef
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Patent number: 6955996Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.Type: GrantFiled: July 22, 2003Date of Patent: October 18, 2005Assignee: Micron Technology, Inc.Inventors: Daniel F Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
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Patent number: 6949477Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.Type: GrantFiled: August 14, 2003Date of Patent: September 27, 2005Assignee: Micron Technology, Inc.Inventors: Ronald A. Weimer, Scott J. DeBoer, Dan Gealy, Husam N. Al-Shareef
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Patent number: 6943392Abstract: The invention comprises capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen. In one embodiment, a capacitor includes first and second conductive electrodes having a high k capacitor dielectric region positioned therebetween. The high k capacitor dielectric region includes a layer of metal oxide having multiple different metals bonded with oxygen. The layer has varying stoichiometry across its thickness. The layer includes an inner region, a middle region, and an outer region. The middle region has a different stoichiometry than both the inner and outer regions.Type: GrantFiled: August 30, 1999Date of Patent: September 13, 2005Assignee: Micron Technology, Inc.Inventors: Vishnu K. Agarwal, Husam N. Al-Shareef
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Patent number: 6872639Abstract: An integrated circuit has a multi-layer stack such as a gate stack or a digit line stack disposed on a layer comprising silicon. A conductive film is formed on the transition metal boride layer. A process for fabricating such devices can include forming the conductive film using a vapor deposition process with a reaction gas comprising fluorine. In the case of a gate stack, the transition metal boride layer can help reduce or eliminate the diffusion of fluorine atoms from the conductive film into a gate dielectric layer. Similarly, in the case of digit line stacks as well as gate stacks, the transition metal boride layer can reduce the diffusion of silicon from the polysilicon layer into the conductive film to help maintain a low resistance for the conductive film.Type: GrantFiled: April 17, 2003Date of Patent: March 29, 2005Assignee: Micron Technology, Inc.Inventors: Scott J. DeBoer, Husam N. Al-Shareef
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Patent number: 6864527Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.Type: GrantFiled: August 29, 2002Date of Patent: March 8, 2005Assignee: Micron Technology, Inc.Inventors: Scott Jeffrey DeBoer, Husam N. Al-Shareef, Randhir P. S. Thakur, Dan Gealy
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Patent number: 6827790Abstract: a method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five (5) atmospheres to twenty-five (25) atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, rhodium, nickel, silver, and gold.Type: GrantFiled: March 2, 2001Date of Patent: December 7, 2004Assignee: Micron Technology, Inc.Inventors: Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
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Publication number: 20040185677Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.Type: ApplicationFiled: July 22, 2003Publication date: September 23, 2004Inventors: F. Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
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Patent number: 6773981Abstract: Capacitors and methods of forming capacitors are disclosed. In one implementation, a capacitor comprises a capacitor dielectric layer comprising Ta2O5 formed over a first capacitor electrode. A second capacitor electrode is formed over the Ta2O5 capacitor dielectric layer. Preferably, at least a portion of the second capacitor electrode is formed over and in contact with the Ta2O5 in an oxygen containing environment at a temperature of at least about 175° C. Chemical vapor deposition is one example forming method. The preferred second capacitor electrode comprises a conductive metal oxide. A more preferred second capacitor electrode comprises a conductive silicon comprising layer, over a conductive titanium comprising layer, over a conductive metal oxide layer. A preferred first capacitor electrode comprises a conductively doped Si—Ge alloy. Preferably, a Si3N4 layer is formed over the first capacitor electrode. DRAM cells and methods of forming DRAM cells are disclosed.Type: GrantFiled: August 2, 2000Date of Patent: August 10, 2004Assignee: Micron Technology, Inc.Inventors: Husam N. Al-Shareef, Scott Jeffrey DeBoer, F. Daniel Gealy, Randhir P. S. Thakur
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Patent number: 6720607Abstract: A method for ion implantation of high dielectric constant materials with dopants to reduce film leakage and improve resistance degradation is disclosed. Particularly, the invention relates to ion implantation of (Ba,Sr)TiO3 (BST) with donor dopants to reduce film leakage and improve resistance degradation of the BST film. The invention also relates to varying the ion implantation angle of the dopant to uniformly dope the high dielectric constant materials when they have been fabricated over a stepped structure. The invention also relates to integrated circuits having a doped thin film high dielectric material used as an insulating layer in a capacitor structure.Type: GrantFiled: November 6, 2000Date of Patent: April 13, 2004Assignee: Micron Technology, Inc.Inventors: Cem Basceri, Husam N. Al-Shareef
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Patent number: 6673689Abstract: A high surface area capacitor comprising a double metal layer of an electrode metal and a barrier material deposited on hemispherical grain (HSG) silicon and a high dielectric constant (HDC) material deposited over the double metal layer. An upper cell plate electrode is deposited over the HDC material. The double metal layer preferably comprises one noble metal for the electrode metal and an oxidizable metal for the barrier material. The noble metal alone would normally allow oxygen to diffuse into and oxidize any adhesion layer and/or undesirably oxidize any silicon-containing material during the deposition of the HDC material. The barrier metal is used to form a conducting oxide layer or a conducting layer which stops the oxygen diffusion. The HSG polysilicon provides a surface roughness that boosts cell capacitance. The HDC material is also used to boost cell capacitance.Type: GrantFiled: May 30, 2002Date of Patent: January 6, 2004Assignee: Micron Technology, Inc.Inventors: Husam N. Al-Shareef, Scott DeBoer, Randhir Thakur
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Publication number: 20030203608Abstract: An integrated circuit has a multi-layer stack such as a gate stack or a digit line stack disposed on a layer comprising silicon. A conductive film is formed on the transition metal boride layer. A process for fabricating such devices can include forming the conductive film using a vapor deposition process with a reaction gas comprising fluorine. In the case of a gate stack, the transition metal boride layer can help reduce or eliminate the diffusion of fluorine atoms from the conductive film into a gate dielectric layer. Similarly, in the case of digit line stacks as well as gate stacks, the transition metal boride layer can reduce the diffusion of silicon from the polysilicon layer into the conductive film to help maintain a low resistance for the conductive film.Type: ApplicationFiled: April 17, 2003Publication date: October 30, 2003Inventors: Scott J. DeBoer, Husam N. Al-Shareef
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Patent number: 6614082Abstract: An integrated circuit has a multi-layer stack such as a gate stack or a digit line stack disposed on a layer comprising silicon. A conductive film is formed on the transition metal boride layer. A process for fabricating such devices can include forming the conductive film using a vapor deposition process with a reaction gas comprising fluorine. In the case of a gate stack, the transition metal boride layer can help reduce or eliminate the diffusion of fluorine atoms from the conductive film into a gate dielectric layer. Similarly, in the case of digit line stacks as well as gate stacks, the transition metal boride layer can reduce the diffusion of silicon from the polysilicon layer into the conductive film to help maintain a low resistance for the conductive film.Type: GrantFiled: January 29, 1999Date of Patent: September 2, 2003Assignee: Micron Technology, Inc.Inventors: Scott J. DeBoer, Husam N. Al-Shareef