Patents by Inventor Husam N. Al-Shareef

Husam N. Al-Shareef has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6613654
    Abstract: An integrated circuit has a multi-layer stack such as a gate stack or a digit line stack disposed on a layer comprising silicon. A conductive film is formed on the transition metal boride layer. A process for fabricating such devices can include forming the conductive film using a vapor deposition process with a reaction gas comprising fluorine. In the case of a gate stack, the transition metal boride layer can help reduce or eliminate the diffusion of fluorine atoms from the conductive film into a gate dielectric layer. Similarly, in the case of digit line stacks as well as gate stacks, the transition metal boride layer can reduce the diffusion of silicon from the polysilicon layer into the conductive film to help maintain a low resistance for the conductive film.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: September 2, 2003
    Inventors: Scott J. DeBoer, Husam N. Al-Shareef
  • Patent number: 6610211
    Abstract: The invention encompasses methods of processing internal surfaces of a chemical vapor deposition reactor. In one implementation, material is deposited over internal surfaces of a chemical vapor deposition reactor while processing semiconductor substrates therein. The deposited material is treated with atomic oxygen. After the treating, at least some of the deposited material is etched from the reactor internal surfaces. In one embodiment, first etching is conducted of some of the deposited material from the reactor internal surfaces. After the first etching, remaining deposited material is treated with atomic oxygen. After the treating, second etching is conducted of at least some of the remaining deposited material from the reactor internal surfaces. In one embodiment, the deposited material is first treated with atomic oxygen. After the first treating, first etching is conducted of some of the deposited material from the reactor internal surfaces.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: August 26, 2003
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Husam N. Al-Shareef, Scott Jeffrey DeBoer
  • Patent number: 6596651
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: July 22, 2003
    Assignee: Micron Technology, Inc.
    Inventors: F. Daniel Gealy, Scott DeBoer, Dave Chapek, Husam N. Al-Shareef, Randhir Thakur
  • Patent number: 6518121
    Abstract: Titanium boride (TiBx), zirconium boride (ZrBx) and hafnium boride (HfBx) barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The barriers protect cell dielectrics from diffusion and other interaction with surrounding materials during subsequent thermal processing.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: February 11, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Husam N. Al-Shareef, Scott J. DeBoer, Dan Gealy, Randhir P. S. Thakur
  • Publication number: 20030015769
    Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.
    Type: Application
    Filed: August 29, 2002
    Publication date: January 23, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Scott Jeffrey DeBoer, Husam N. Al-Shareef, Randhir P.S. Thakur, Dan Gealy
  • Publication number: 20030001194
    Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.
    Type: Application
    Filed: August 29, 2002
    Publication date: January 2, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Scott Jeffrey DeBoer, Husam N. Al-Shareef, Randhir P.S. Thakur, Dan Gealy
  • Publication number: 20020192978
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Application
    Filed: August 5, 2002
    Publication date: December 19, 2002
    Inventors: F. Daniel Gealy, Scott DeBoer, Dave Chapek, Husam N. Al-Shareef, Randhir Thakur
  • Publication number: 20020155658
    Abstract: A high surface area capacitor comprising a double metal layer of an electrode metal and a barrier material deposited on hemispherical grain (HSG) silicon and a high dielectric constant (HDC) material deposited over the double metal layer. An upper cell plate electrode is deposited over the HDC material. The double metal layer preferably comprises one noble metal for the electrode metal and an oxidizable metal for the barrier material. The noble metal alone would normally allow oxygen to diffuse into and oxidize any adhesion layer and/or undesirably oxidize any silicon-containing material during the deposition of the HDC material. The barrier metal is used to form a conducting oxide layer or a conducting layer which stops the oxygen diffusion. The HSG polysilicon provides a surface roughness that boosts cell capacitance. The HDC material is also used to boost cell capacitance.
    Type: Application
    Filed: May 30, 2002
    Publication date: October 24, 2002
    Inventors: Husam N. Al-Shareef, Scott DeBoer, Randhir Thakur
  • Publication number: 20020151107
    Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.
    Type: Application
    Filed: April 29, 2002
    Publication date: October 17, 2002
    Inventors: Ronald A. Weimer, Scott J. DeBoer, Dan Gealy, Husam N. Al-Shareef
  • Patent number: 6458645
    Abstract: A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: October 1, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Scott Jeffrey DeBoer, Husam N. Al-Shareef, Randhir P. S. Thakur, Dan Gealy
  • Patent number: 6423649
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: July 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur
  • Publication number: 20020079531
    Abstract: Titanium boride (TiBx), zirconium boride (ZrBx) and hafnium boride (HfBx) barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The barriers protect cell dielectrics from diffusion and other interaction with surrounding materials during subsequent thermal processing.
    Type: Application
    Filed: August 30, 2001
    Publication date: June 27, 2002
    Inventors: Husam N. Al-Shareef, Scott J. DeBoer, Dan Gealy, Randir P.S. Thakur
  • Patent number: 6400552
    Abstract: Capacitors and methods of forming capacitors are disclosed. In one implementation, a capacitor includes a capacitor dielectric layer including Ta2O5 formed over a first capacitor electrode. A second capacitor electrode is formed over the Ta2O5 capacitor dielectric layer. Preferably, at least a portion of the second capacitor electrode is formed over and in contact with the Ta2O5 in an oxygen containing environment at a temperature of at least about 175° C. Chemical vapor deposition is one example forming method. The preferred second capacitor electrode includes a conductive metal oxide. A more preferred second capacitor electrode includes a conductive silicon including layer, over a conductive titanium including layer, over a conductive metal oxide layer. A preferred first capacitor electrode includes a conductively doped Si—Ge alloy. Preferably, a Si3N4 layer is formed over the first capacitor electrode. DRAM cells and methods of forming DRAM cells are disclosed.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: June 4, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Husam N. Al-Shareef, Scott Jeffrey DeBoer, F. Daniel Gealy, Randhir P. S. Thakur
  • Patent number: 6399459
    Abstract: A high surface area capacitor comprising a double metal layer (an electrode metal and barrier material) deposited on hemispherical grain (HSG) silicon, wherein a high dielectric constant (HDC) material is deposited over the double metal layer. The high surface area capacitor is complete with an upper cell plate electrode deposited over the HDC material. The double metal layer preferably comprises one noble metal, such as platinum or palladium, for the electrode metal and an oxidizable metal, such as ruthenium, iridium, or molybdenum, for the barrier material. The noble metal, such as platinum metal, alone would normally allow oxygen to diffuse into and oxidize any adhesion layer (making the adhesion layer less conductive) and/or undesirably oxidize any silicon-containing material during the deposition of the HDC material. Thus, the barrier metal is used to form a conducting oxide layer or a conducting layer which stops the oxygen diffusion.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: June 4, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Husam N. Al-Shareef, Scott DeBoer, Randhir Thakur
  • Publication number: 20020045358
    Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.
    Type: Application
    Filed: July 26, 2001
    Publication date: April 18, 2002
    Inventors: Ronald A. Weimer, Scott J. DeBoer, Dan Gealy, Husam N. Al-Shareef
  • Patent number: 6351005
    Abstract: An integrated capacitor is provided, incorporating a high dielectric constant material. In a disclosed method, a high k capacitor dielectric is formed in the shape of a container above a protective layer. After the dielectric is formed, inner and outer electrodes are formed, representing storage and reference electrodes of a memory cell. Contact is separately made through the protective layer from a storage electrode layer, which lines the inner surface of the dielectric, to an underlying polysilicon plug. The contact can be a thin layer lining the interior of the storage electrode layer, or can completely fill the container capacitor. In the latter instance, the contact can form part of the storage electrode and contribute to capacitance of the cell. Volatile dielectric materials can thus be formed prior to the electrodes, avoiding oxidation of the electrodes and underlying polysilicon plug, while also minimizing oxygen depletion through diffusion from the high dielectric constant material.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: February 26, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Husam N. Al-Shareef, Er-Xuan Ping
  • Publication number: 20010054733
    Abstract: The invention comprises capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen. In one embodiment, a capacitor includes first and second conductive electrodes having a high k capacitor dielectric region positioned therebetween. The high k capacitor dielectric region includes a layer of metal oxide having multiple different metals bonded with oxygen. The layer has varying stoichiometry across its thickness. The layer includes an inner region, a middle region, and an outer region. The middle region has a different stoichiometry than both the inner and outer regions.
    Type: Application
    Filed: August 30, 1999
    Publication date: December 27, 2001
    Inventors: VISHNU AGARWAL, HUSAM N. AL-SHAREEF
  • Publication number: 20010053057
    Abstract: Capacitors and methods of forming capacitors are disclosed. In one implementation, a capacitor comprises a capacitor dielectric layer comprising Ta2O5 formed over a first capacitor electrode. A second capacitor electrode is formed over the Ta2O5 capacitor dielectric layer. Preferably, at least a portion of the second capacitor electrode is formed over and in contact with the Ta2O5 in an oxygen containing environment at a temperature of at least about 175° C. Chemical vapor deposition is one example forming method. The preferred second capacitor electrode comprises a conductive metal oxide. A more preferred second capacitor electrode comprises a conductive silicon comprising layer, over a conductive titanium comprising layer, over a conductive metal oxide layer. A preferred first capacitor electrode comprises a conductively doped Si—Ge alloy. Preferably, a Si3N4 layer is formed over the first capacitor electrode. DRAM cells and methods of forming DRAM cells are disclosed.
    Type: Application
    Filed: April 30, 2001
    Publication date: December 20, 2001
    Inventors: Husam N. Al-Shareef, Scott Jeffrey DeBoer, F. Daniel Gealy, Randhir P. S. Thakur
  • Publication number: 20010051406
    Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.
    Type: Application
    Filed: April 22, 1999
    Publication date: December 13, 2001
    Inventors: RONALD A. WEIMER, SCOTT J. DEBOER, DAN GEALY, HUSAM N. AL-SHAREEF
  • Publication number: 20010044219
    Abstract: A method and apparatus for preventing N2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus utilize a catalyst to catalytically disassociate N2O as it enters the high pressure oxidation furnace. This catalyst is used in an environment of between five atmospheres and 25 atmospheres N2O and a temperature range of 600° to 750° C., which are the conditions that lead to the N2O going super critical. By preventing the N2O from becoming super critical, the reaction is controlled that prevents both temperature and pressure spikes. The catalyst can be selected from the group of noble transition metals and their oxides. This group can comprise palladium, platinum, iridium, rhodium, nickel, silver, and gold.
    Type: Application
    Filed: July 20, 2001
    Publication date: November 22, 2001
    Inventors: F. Daniel Gealy, Dave Chapek, Scott DeBoer, Husam N. Al-Shareef, Randhir Thakur