Abstract: An electronic device including an optical module, a method of operating the electronic device including the optical module, and a non-transitory computer-readable recording medium having recorded thereon a program for performing the method. The electronic device includes an optical module configured to project content on a projection surface and a processor configured to determine whether the electronic device is positioned within a predetermined range of a projection surface and control the optical module to project the content onto the projection surface based on the determination.

Abstract: The present invention includes an expression cassette containing a polynucleotide encoding a polypeptide; and a host cell, transgenic plant (e.g., a dicot or monocot), transformed seed, and transgenic rootstock containing said expression cassette. Methods for desensitizing a plant to endogenous cytokinin; increasing seed, embryo or cotyledon size or weight; increasing the seed yield of a plant; and/or increasing the size of the root or root meristem or formation of lateral or adventitious roots are provided. In some embodiments, expression of the polypeptide is under control of a seed-preferred, embryo-preferred or root-preferred promoter.

Abstract: Disclosed are a method, system, and recording medium for connecting a public transportation route service and a map service. A map providing method includes providing a mode switching function at a first service that provides a public transportation map and a second service that provides a road map, and switching a service mode to the public transportation map or the road map through interconnection between the first service and the second service in response to executing the mode switching function.

Abstract: A zoom control method includes identifying or receiving position information including a current position or a departure position associated with a user, displaying a transportation route map or a road map including the position information on a display of a terminal, determining that a preset period of time has elapsed from a display point in time, and displaying the transportation route map or the road map on the display of the terminal through an auto zoom-out or an auto zoom-in, wherein the displaying of the transportation route map or the road map on the display of the terminal through the auto zoom-out or the auto zoom-in includes marking the position information on the auto zoomed-out or zoomed-in transportation route map or road map.

Abstract: Disclosed is a method and system for providing a route search service based on a public transportation map, such as a subway map, a bus map, a rail map, etc. A route search service providing method includes searching for a route from a departure location to a destination using public transportation in response to a route search request, providing a screen displaying the found route on a public transportation map, determining a movement direction of the public transportation map in response to a user input for changing the found route, moving and providing the public transportation map along the movement direction on the screen, changing the departure location or the destination with a point selected on the moved public transportation map, searching again for the route based on the changed departure location or destination, and changing the screen including the moved public transportation map with a screen displaying the route found through a re-search, on the public transportation map.

Abstract: A multilayer ceramic electronic component includes a ceramic body having a plurality of dielectric layers and internal electrodes having lead portions narrower than capacitance portions, the first and second external electrodes and dummy electrodes, wherein the first and second external electrodes disposed on both end surfaces of the ceramic body in the length direction, to be connected to the first and second lead portions, respectively, and dummy electrodes disposed on positions of margin portions of the dielectric layers corresponding to the first and second lead portions, to be spaced apart from the first and second internal electrodes, in a width direction of the ceramic body.

Abstract: A search result providing method implemented in a computer includes providing a search result screen including a search result of a first keyword in response to a search request for the first keyword, and additionally providing a search result of a second keyword on the search result screen in response to a search request for at least one second keyword different from the first keyword.

Abstract: A multilayer ceramic electronic component may include: a ceramic body in which dielectric layers containing plate-shaped dielectric grains are stacked; and internal electrodes disposed on the dielectric layers within the ceramic body. The dielectric layer may contain dielectric grains, plate-shaped surfaces of which have an angle of 20° or less with regard to a boundary surface between the dielectric layer and the internal electrode.

Abstract: A method of manufacturing a vertical-cell-type semiconductor device may include stacking alternately first insulating layers and second insulating layers on a substrate, forming a channel hole through the first and second insulating layers, and forming dielectric layers. A channel layer and a gap fill pattern may be formed within the channel hole. The channel layer may cover a top surface of an uppermost first insulating layer. The top surface of the gap fill pattern is at the same level with the top surface of the channel layer. A first conductivity type impurities may be implanted into the channel layer to form a channel impurity region. A top surface of the gap fill pattern may be recessed. A contact pad on the recessed surface of the gap fill pattern may be formed. A ground selection gate electrode, cell gate electrodes, and string selection gate electrodes may be formed in interlayer spaces that be formed by removing the second insulating layers.

Abstract: There are provided a multilayer ceramic electronic component and a method of manufacturing the same. Here, an average diameter (Dc) of ceramic grains in a cover area is smaller than an average diameter (Da) of ceramic grains in the active area, and when a thickness of the cover area is expressed by Tc, 9 um?Tc?25 um and Tc/Dc?55 are satisfied. A multilayer ceramic capacitor having excellent moisture-resistance properties may be obtained.

Abstract: The present disclosure relates to a superconducting rotating electrical machine and a manufacturing method for a high temperature superconducting film thereof. The superconducting rotating electrical machine includes a stator, and a rotor rotatable with respect to the stator, the rotor having a rotary shaft and a rotor winding. Here, the rotor winding includes tubes disposed on a circumference of the rotary shaft and each forming a passage for a cooling fluid therein, superconducting wires accommodated within the tubes, and a cooling fluid flowing through the inside of the tubes. This configuration may allow for direct heat exchange between the superconducting wires and a refrigerant, resulting in improvement of heat exchange efficiencies of the superconducting wires.

Abstract: According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.

Abstract: The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern.

Abstract: There is provided a dielectric composition containing barium calcium tin titanate powder composed of (Ba(1-x-y)CaxSny)zTiO3, satisfying 0.01?x?0.15, 0.01?y?0.20, and 0.99?z?1.01.

Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.

Abstract: An example embodiment relates to a method including forming a bottom electrode and an insulating layer on a substrate, the insulating layer defining a first opening that exposes a portion of the bottom electrode. The method includes forming a variable resistance material pattern, including a plurality of elements, to fill the first opening. The variable resistance material pattern may be doped with a dopant that includes at least one of the plurality of elements in the variable resistance material pattern. The method includes forming a top electrode on the variable resistance material pattern.

Abstract: A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.

Abstract: A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.

Abstract: According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.

Abstract: The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern.