Abstract: According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.

Abstract: A first insulating interlayer is formed on a substrate including first and second regions. The first insulating interlayer has top surface, a height of which is greater in the first region than in the second region. A first planarization stop layer and a second insulating interlayer are formed. The second insulating interlayer is planarized until the first planarization stop layer is exposed. The first planarization stop layer and the first and second insulating interlayers in the second region are removed to expose the substrate. A lower mold structure including first insulation layer patterns, first sacrificial layer patterns and a second planarization stop layer pattern is formed. The first insulation layer patterns and the first sacrificial layer patterns are alternately and repeatedly formed on the substrate, and a second planarization stop layer pattern is formed on the first insulation layer pattern.

Abstract: Disclosed is a multilayer ceramic capacitor. The multilayer ceramic capacitor includes a capacitive part including a plurality of dielectric layers and first and second internal electrodes that are laminated in an alternating manner, wherein one set of ends of the first internal electrodes and the other set of ends of the second internal electrodes are exposed in a lamination direction in which the dielectric layers are laminated, a protective layer formed on at least one of top and bottom surfaces of the capacitive part, including a plurality of pores having an average pore size of 0.5 ?m to 3 ?m, and having a porosity of 2% to 10%, and first and second external electrodes electrically connected to the first and second internal electrodes exposed in the lamination direction of the dielectric layers.

Abstract: According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.

Abstract: Disclosed is multilayer ceramic capacitor. The multilayer ceramic capacitor includes a capacitive part including dielectric layers and first and second internal electrodes alternately laminated therein, wherein the dielectric layers include first ceramic particles having an average particle size of 0.1 ?m to 0.3 ?m, and one set of ends of the first internal electrodes and one set of ends of the second internal electrodes are exposed in a lamination direction of the dielectric layers, a protective layer formed on at least one of top and bottom surfaces of the capacitive part, including second ceramic particles and having a porosity of 2% to 4%, wherein an average particle size ratio of the second ceramic particles to the first ceramic particles ranges from 1.1 to 1.3; and first and second external electrodes electrically connected to the first and second internal electrodes exposed in the lamination direction of the dielectric layers.

Abstract: There are provided phosphors having high luminous efficiency at desired wavelengths and good light output stability and a light emitting device using the same. A phosphor according to an aspect of the invention includes a sulfide crystallographic phase and an oxide crystallographic phase. Here, the phosphor is a multiphase compound in which the sulfide crystallographic phase and the oxide crystallographic phase exist together.

Abstract: There is provided a multilayer ceramic capacitor including: a capacitor main body formed by stacking a dielectric layer having a thickness of td and alternately stacking more than one opposing pair of a first internal electrode having a thickness of te and a second internal electrode having the same thickness as the first internal electrode, and having the dielectric layer therebetween; and a protective layer formed by stacking a second dielectric layer on at least one of an upper surface and a lower surface of the capacitor main body so that a dielectric material layer has a thickness of tc, wherein when a thickness from an end of a region where the first internal electrode and the second internal electrode oppose each other to side and end surfaces of the capacitor main body is a, it satisfies the following Equation 1 and a method of fabricating a multilayer ceramic capacitor are provided.

Abstract: Disclosed are a method of manufacturing multilayer ceramic electronic components and a multilayer ceramic electronic component using the same. There is provided a method of preparing a plurality of ceramic layers including a first side, a second side, a third side, and a fourth side; printing a first inner electrode pattern and a second inner electrode pattern on the ceramic layers, the first inner electrode pattern and the second inner electrode pattern being exposed to the first side or the third side and having concave portions in the second side and fourth side directions; and stacking and compressing the plurality of ceramic layers printed with the first inner electrode pattern and the second inner electrode pattern.

Abstract: An example embodiment relates to a method including forming a bottom electrode and an insulating layer on a substrate, the insulating layer defining a first opening that exposes a portion of the bottom electrode. The method includes forming a variable resistance material pattern, including a plurality of elements, to fill the first opening. The variable resistance material pattern may be doped with a dopant that includes at least one of the plurality of elements in the variable resistance material pattern. The method includes forming a top electrode on the variable resistance material pattern.

Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.

Abstract: A multilayer ceramic capacitor includes a capacitor body in which inner electrodes and dielectric layers are alternately laminated, and a length difference rate (D) of the inner electrodes is 7% or less. The length difference rate (D) is defined by D={L?1}/L×100, where L is a maximum length of the inner electrode, and l is a minimum length of the inner electrode.

Abstract: A method of fabricating a three-dimensional semiconductor memory device includes providing a substrate which includes a cell array region and a peripheral region. The method further includes a peripheral structure on the peripheral region of the substrate, where the peripheral structure includes peripheral circuits and is configured to expose the cell array region of the substrate. The method further includes forming a lower cell structure on the cell array region of the substrate, forming an insulating layer to cover the peripheral structure and the lower cell structure on the substrate, planarizing the insulating layer using top surfaces of the peripheral structure and the lower cell structure as a planarization stop layer, and forming an upper cell structure on the lower cell structure.

Abstract: There is provided a method of measuring deformation of a laminated body, the method including: laminating and pressurizing a plurality of green sheets each having a plurality of inner electrodes arranged therein to form a laminated body having a plurality of unit chips arranged therein; marking location information of each of the unit chips on an XY plane of the laminated body on a surface of the unit chip; cutting the laminated body into the plurality of unit chips; measuring a deformation level of each of the cut unit chips; and storing the deformation level measured from the each of the cut unit chips to correspond to the location information of the unit chip.

Abstract: The present invention relates to a method for producing plants with improved or suppressed blue light recognition capabilities.

Abstract: A multilayer ceramic capacitor includes a capacitor body in which inner electrodes and dielectric layers are alternately laminated, and a length difference rate (D) of the inner electrodes is 7% or less. The length difference rate (D) is defined by D={L?1}/L×100, where L is a maximum length of the inner electrode, and l is a minimum length of the inner electrode.

Abstract: There is provided a multilayer ceramic capacitor including: a capacitor main body formed by stacking a dielectric layer having a thickness of td and alternately stacking more than one opposing pair of a first internal electrode having a thickness of to and a second internal electrode having the same thickness as the first internal electrode, and having the dielectric layer therebetween; and a protective layer formed by stacking a second dielectric layer on at least one of an upper surface and a lower surface of the capacitor main body so that a dielectric material layer has a thickness of tc, wherein when a thickness from an end of a region where the first internal electrode and the second internal electrode oppose each other to side and end surfaces of the capacitor main body is a, it satisfies the following Equation 1 and a method of fabricating a multilayer ceramic capacitor are provided.

Abstract: A multilayer ceramic capacitor includes: an effective layer formed by alternately laminating inner electrodes and dielectric layers; and a protection layer formed by stacking dielectric layers on upper and lower surfaces of the effective layer, wherein the thickness of the protection layer is 10.0 to 30.0 times the sum of an average thickness of the inner electrodes and an average thickness of the dielectric layers within the effective layer.

Abstract: Disclosed is multilayer ceramic capacitor. The multilayer ceramic capacitor includes a capacitive part including dielectric layers and first and second internal electrodes alternately laminated therein, wherein the dielectric layers include first ceramic particles having an average particle size of 0.1 ?m to 0.3 ?m, and one set of ends of the first internal electrodes and one set of ends of the second internal electrodes are exposed in a lamination direction of the dielectric layers, a protective layer formed on at least one of top and bottom surfaces of the capacitive part, including second ceramic particles and having a porosity of 2% to 4%, wherein an average particle size ratio of the second ceramic particles to the first ceramic particles ranges from 1.1 to 1.3; and first and second external electrodes electrically connected to the first and second internal electrodes exposed in the lamination direction of the dielectric layers.

Abstract: Disclosed is a multilayer ceramic capacitor. The multilayer ceramic capacitor includes a capacitive part including a plurality of dielectric layers and first and second internal electrodes that are laminated in an alternating manner, wherein one set of ends of the first internal electrodes and the other set of ends of the second internal electrodes are exposed in a lamination direction in which the dielectric layers are laminated, a protective layer formed on at least one of top and bottom surfaces of the capacitive part, including a plurality of pores having an average pore size of 0.5 ?m to 3 ?m, and having a porosity of 2% to 10%, and first and second external electrodes electrically connected to the first and second internal electrodes exposed in the lamination direction of the dielectric layers.

Abstract: A transmission for a tractor has a main transmission part between a forward/reverse transmission part and a sub transmission part. The main transmission part has a driving shaft, a first sub shaft parallel with the driving shaft, a second sub shaft parallel with the first sub shaft, an output shaft arranged between the first sub shaft and the second sub shaft, first and second driving gears installed spaced to a distance from each other, third and fourth driving gears installed spaced to a distance from each other, a first output gear installed on the output shaft, a second output gear installed on the output shaft, a first clutch arranged between the first driving gear and the second driving gear, and a second clutch arranged between the third driving gear and the fourth driving gear.