Patents by Inventor Hyoung-Seub Rhie

Hyoung-Seub Rhie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230268447
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 24, 2023
    Inventor: Hyoung Seub RHIE
  • Patent number: 11664463
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: May 30, 2023
    Assignee: Mosaid Technologies Incorporated
    Inventor: Hyoung Seub Rhie
  • Publication number: 20210408301
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Application
    Filed: July 7, 2021
    Publication date: December 30, 2021
    Inventor: Hyoung Seub Rhie
  • Publication number: 20210295923
    Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.
    Type: Application
    Filed: April 7, 2021
    Publication date: September 23, 2021
    Inventor: Hyoung Seub RHIE
  • Patent number: 11088289
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: August 10, 2021
    Assignee: Mosaid Technologies Incorporated
    Inventor: Hyoung Seub Rhie
  • Patent number: 10998048
    Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 4, 2021
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie
  • Publication number: 20200381566
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Application
    Filed: March 12, 2020
    Publication date: December 3, 2020
    Inventor: Hyoung Seub Rhie
  • Patent number: 10622488
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: April 14, 2020
    Assignee: Conversant intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie
  • Publication number: 20200020401
    Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.
    Type: Application
    Filed: September 24, 2019
    Publication date: January 16, 2020
    Inventor: Hyoung Seub RHIE
  • Publication number: 20190348544
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Inventor: Hyoung Seub Rhie
  • Patent number: 10460807
    Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: October 29, 2019
    Assignee: Conversant Intellectual Property Mangement Inc.
    Inventor: Hyoung Seub Rhie
  • Patent number: 10403766
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 3, 2019
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie
  • Patent number: 10074655
    Abstract: A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a first capacitor plate conductor formed with a cylinder-shaped storage node electrode formed in the multi-layer stack, a capacitor dielectric layer surrounding the cylinder-shaped storage node electrode, and a second capacitor plate conductor formed from a conductive layer in the multi-layer stack that is sandwiched between a bottom and top dielectric layer, where the cylinder-shaped storage node electrode is surrounded by and extends through the conductive layer.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: September 11, 2018
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie
  • Publication number: 20180175044
    Abstract: A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a first capacitor plate conductor formed with a cylinder-shaped storage node electrode formed in the multi-layer stack, a capacitor dielectric layer surrounding the cylinder-shaped storage node electrode, and a second capacitor plate conductor formed from a conductive layer in the multi-layer stack that is sandwiched between a bottom and top dielectric layer, where the cylinder-shaped storage node electrode is surrounded by and extends through the conductive layer.
    Type: Application
    Filed: February 20, 2018
    Publication date: June 21, 2018
    Inventor: Hyoung Seub RHIE
  • Patent number: 9935110
    Abstract: A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a first capacitor plate conductor formed with a cylinder-shaped storage node electrode formed in the multi-layer stack, a capacitor dielectric layer surrounding the cylinder-shaped storage node electrode, and a second capacitor plate conductor formed from a conductive layer in the multi-layer stack that is sandwiched between a bottom and top dielectric layer, where the cylinder-shaped storage node electrode is surrounded by and extends through the conductive layer.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: April 3, 2018
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie
  • Patent number: 9893084
    Abstract: A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: February 13, 2018
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie
  • Patent number: 9893076
    Abstract: A three-dimensional integrated circuit nonvolatile memory array includes a memory array of vertical channel NAND flash strings connected between an upper layer connection bit line and a substrate which includes one or more elevated source regions disposed on at least one side of each row of NAND flash strings so that each NAND flash string includes a lower select transistor with a first channel portion that runs perpendicular to the surface of the substrate through a vertical channel string body, a second channel portion that runs parallel to the surface of the substrate, and a third channel portion that runs perpendicular to the surface of the substrate through the elevated source region.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: February 13, 2018
    Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
    Inventor: Hyoung Seub Rhie
  • Publication number: 20180025781
    Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.
    Type: Application
    Filed: June 2, 2017
    Publication date: January 25, 2018
    Inventor: Hyoung Seub RHIE
  • Patent number: RE47816
    Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 14, 2020
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie
  • Patent number: RE48766
    Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 5, 2021
    Assignee: Mosaid Technologies Incorporated
    Inventor: Hyoung Seub Rhie