Abstract: A non-volatile memory system that has junctionless transistors is provided that uses suppression of the formation of an inversion-layer source and drain in the junctionless transistors to cause a discontinuous channel in at least one string. The system may include NAND flash memory cells composed of junctionless transistors, and has a set of wordlines. During program operation, a selected wordline of the set of wordlines is biased at a program voltage, and wordline voltage low enough to suppress the formation of source/drains is applied on at least one word line on a source side of the selected wordline such that a channel isolation occurs thereby causing the discontinuous channel in the at least string.

Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

Abstract: A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address. Row decoding circuitry associated with each group of memory blocks can have a row pitch spacing that is greater than a row pitch spacing of a single memory block and less than or equal to a total row pitch spacing corresponding to the group of memory blocks.

Abstract: A memory device includes a plurality of memory bit lines connected to a plurality of memory cells, a plurality of reference bit lines connected to a plurality of reference cells and a reference bit line selection circuit. The memory bit lines has a first pattern and a second pattern, and the first pattern has a first critical dimension (CD) distribution, and the second pattern has a second CD distribution. The reference bit lines have the first pattern and the second pattern. The reference bit line selection circuit provides a reference signal by selecting a reference bit line having a same pattern as a selected memory bit line connected to a memory cell to be read.

Abstract: A magnetic racetrack memory device includes; a magnetic track having a plurality of magnetic domains partitioned by at least one magnetic domain wall, a current source applying current to the magnetic track sufficient to move the at least one magnetic domain wall and the plurality of magnetic domains along the magnetic track, a writing device disposed at a first location along the magnetic track and storing write data to the magnetic domains, a reading device disposed at a second location along the magnetic track and retrieving read data from the magnetic domains, and a write-back loop connecting the reading device and the writing device and communicating read data obtained by the reading device to the writing device.

Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portions and third portions. The second portions extend in a first direction on the first portion. The second portions are spaced apart from one another in a second direction substantially perpendicular to the first direction. The third portions are provided on the second portions. The third portions are spaced apart from one another in the first and second directions. The first insulating layers cover sidewalls of the second portions. The first conductive layer patterns are provided on the first insulating layers.

Abstract: A memory device includes a plurality of memory bit lines connected to a plurality of memory cells, a plurality of reference bit lines connected to a plurality of reference cells and a reference bit line selection circuit. The memory bit lines has a first pattern and a second pattern, and the first pattern has a first critical dimension (CD) distribution, and the second pattern has a second CD distribution. The reference bit lines have the first pattern and the second pattern. The reference bit line selection circuit provides a reference signal by selecting a reference bit line having a same pattern as a selected memory bit line connected to a memory cell to be read.

Abstract: There is provided a semiconductor memory device including; first and second active areas formed to extend in a first direction on a semiconductor substrate, first and second split word lines formed in a second direction on the semiconductor substrate, a common source line extending between the first and second active areas in the first direction and coupled to the first and second active areas, a first variable resistance element formed on the first active area between the first and second split word lines, a second variable resistance element formed on the second active area between the first and second split word lines, first and second bit lines extending in the first direction and respectively coupled to the first and second variable resistance elements.

Abstract: A magnetic racetrack memory device includes; a magnetic track having a plurality of magnetic domains partitioned by at least one magnetic domain wall, a current source applying current to the magnetic track sufficient to move the at least one magnetic domain wall and the plurality of magnetic domains along the magnetic track, a writing device disposed at a first location along the magnetic track and storing write data to the magnetic domains, a reading device disposed at a second location along the magnetic track and retrieving read data from the magnetic domains, and a write-back loop connecting the reading device and the writing device and communicating read data obtained by the reading device to the writing device.

Abstract: Memory devices that include a semiconductor substrate defining a data storage area and a peripheral circuit area. A first magnetic memory device is provided in the peripheral area of the semiconductor substrate and is configured to exchange data signals externally. A second magnetic memory device is provided in the data storage area of the semiconductor substrate and is configured to exchange the data signals with the first magnetic memory device. Each portion of the first magnetic memory device and a portion of the second magnetic memory device include a magnetic tunnel junction structure having at least one magnetic layer. Related data storage devices and systems are also provided.

Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portions and third portions. The second portions extend in a first direction on the first portion. The second portions are spaced apart from one another in a second direction substantially perpendicular to the first direction. The third portions are provided on the second portions. The third portions are spaced apart from one another in the first and second directions. The first insulating layers cover sidewalls of the second portions. The first conductive layer patterns are provided on the first insulating layers.

Abstract: Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.

Abstract: In a semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portions and third portions. The second portions extend in a first direction on the first portion. The second portions are spaced apart from one another in a second direction substantially perpendicular to the first direction. The third portions are provided on the second portions. The third portions are spaced apart from one another in the first and second directions. The first insulating layers cover sidewalls of the second portions. The first conductive layer patterns are provided on the first insulating layers.

Abstract: There is provided a semiconductor memory device including; first and second active areas formed to extend in a first direction on a semiconductor substrate, first and second split word lines formed in a second direction on the semiconductor substrate, a common source line extending between the first and second active areas in the first direction and coupled to the first and second active areas, a first variable resistance element formed on the first active area between the first and second split word lines, a second variable resistance element formed on the second active area between the first and second split word lines, first and second bit lines extending in the first direction and respectively coupled to the first and second variable resistance elements.

Abstract: A memory device includes a first memory array having a plurality of rows and columns of multi-bit DRAM cells therein. A redundant memory array is also provided having a plurality of single-bit memory cells therein. These single-bit memory cells are configured to support replacement of a first plurality of multi-bit memory cells within the first memory array, in response to detecting at least one defective multi-bit memory cell within the first plurality of multi-bit memory cells. This first plurality of multi-bit memory cells may be a column or row of multi-bit memory cells containing at least one defective multi-bit memory cell therein.

Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portions and third portions. The second portions extend in a first direction on the first portion. The second portions are spaced apart from one another in a second direction substantially perpendicular to the first direction. The third portions are provided on the second portions. The third portions are spaced apart from one another in the first and second directions. The first insulating layers cover sidewalls of the second portions. The first conductive layer patterns are provided on the first insulating layers.

Abstract: Disclosed are a semiconductor device and a related method of manufacture. The semiconductor device comprises a semiconductor substrate, a conductive structure including contact regions and gate structures formed on the semiconductor substrate, a protection layer formed on the gate structures, an insulation layer formed on the protection layer, and a plurality of contacts directly contacting the contact regions and the semiconductor substrate through the insulation layer, wherein the contacts have substantially different heights from each other.