Abstract: A semiconductor device includes a first substrate structure having a first substrate, circuit elements disposed on the first substrate, and first bonding pads disposed on the circuit elements. A second substrate structure is connected to the first substrate structure. The second substrate structure includes a second substrate having first and second surfaces, first and second conductive layers spaced apart from each other, a pad insulating layer having an opening exposing a portion of the second conductive layer and gate electrodes stacked to be spaced apart from each other in a first direction and electrically connected to the circuit elements. First contact plugs extend on the second surface in the first direction and connect to the gate electrodes. A second contact plug extends on the second surface in the first direction and electrically connects to the second conductive layer. Second bonding pads electrically connect to the first and second contact plugs.

Abstract: A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the first bonding pad.

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

Abstract: A semiconductor device includes a first substrate structure having a first substrate, circuit elements disposed on the first substrate, and first bonding pads disposed on the circuit elements. A second substrate structure is connected to the first substrate structure. The second substrate structure includes a second substrate having first and second surfaces, first and second conductive layers spaced apart from each other, a pad insulating layer having an opening exposing a portion of the second conductive layer and gate electrodes stacked to be spaced apart from each other in a first direction and electrically connected to the circuit elements. First contact plugs extend on the second surface in the first direction and connect to the gate electrodes. A second contact plug extends on the second surface in the first direction and electrically connects to the second conductive layer. Second bonding pads electrically connect to the first and second contact plugs.

Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

Abstract: A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.

Abstract: A storage device including: a memory controller configured to output user data received from outside of the storage device in a write operation mode and receive read data in a read operation mode; and a memory device including a memory cell array and a random input and output (I/O) engine, the random I/O engine configured to encode the user data provided from the memory controller using a random I/O code, in the write operation mode, and to generate the read data by decoding internal read data read by a data I/O circuit from the memory cell array using the random I/O code, in the read operation mode.

Abstract: A semiconductor device includes a first substrate structure having a first substrate, circuit elements disposed on the first substrate, and first bonding pads disposed on the circuit elements. A second substrate structure is connected to the first substrate structure. The second substrate structure includes a second substrate having first and second surfaces, first and second conductive layers spaced apart from each other, a pad insulating layer having an opening exposing a portion of the second conductive layer and gate electrodes stacked to be spaced apart from each other in a first direction and electrically connected to the circuit elements. First contact plugs extend on the second surface in the first direction and connect to the gate electrodes. A second contact plug extends on the second surface in the first direction and electrically connects to the second conductive layer. Second bonding pads electrically connect to the first and second contact plugs.

Abstract: In a method of aligning wafers, a second wafer having at least one second alignment key may be arranged over a first wafer having at least one first alignment key. At least one alignment hole may be formed by passing through the second wafer to expose the second alignment key and the first alignment key. The first wafer and the second wafer may be aligned with each other using the first alignment key and the second alignment key exposed through the alignment hole. Thus, the first alignment key and the second alignment key exposed through the alignment hole may be positioned at a same vertical line to accurately align the first wafer with the second wafer.

Abstract: A three-dimensional semiconductor device includes: a substrate having a cell array region and a contact region; a stacked structure including a plurality of electrodes and a plurality of electrode isolation insulating layers, which are alternately stacked on the substrate in a vertical direction, and having a stepwise structure on the contact region; vertical structures penetrating the stacked structure in the cell array region, each of the vertical structures constituting a cell string; and word line contact plugs, each penetrating an uppermost electrode among the plurality of electrodes in a region of each of tread portions of the stacked structure having the stepwise structure, being connected to another electrode under the penetrated uppermost electrode, and being electrically insulated from the penetrated uppermost electrode.

Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the first bonding pad.

Abstract: A semiconductor device includes a first substrate structure and a second substrate structure. The first substrate structure includes a base substrate, circuit elements disposed on the base substrate, a first substrate disposed on the circuit elements, first memory cells disposed on the first substrate and electrically connected to the circuit elements, first bit lines disposed on the first memory cells and connected to the first memory cells, and first bonding pads disposed on the first bit lines to be connected to the first bit lines, respectively. The second substrate structure is connected to the first substrate structure on the first substrate structure, and includes a second substrate, second memory cells disposed on the second substrate, second bit lines disposed on the second memory cells and connected to the second memory cells, and second bonding pads disposed on the second bit lines to be connected to the second bit lines, respectively.

Abstract: A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.

Abstract: A three-dimensional semiconductor device includes: a substrate having a cell array region and a contact region; a stacked structure including a plurality of electrodes and a plurality of electrode isolation insulating layers, which are alternately stacked on the substrate in a vertical direction, and having a stepwise structure on the contact region; vertical structures penetrating the stacked structure in the cell array region, each of the vertical structures constituting a cell string; and word line contact plugs, each penetrating an uppermost electrode among the plurality of electrodes in a region of each of tread portions of the stacked structure having the stepwise structure, being connected to another electrode under the penetrated uppermost electrode, and being electrically insulated from the penetrated uppermost electrode.

Abstract: A three-dimensional semiconductor device includes: a substrate having a cell array region and a contact region; a stacked structure including a plurality of electrodes and a plurality of electrode isolation insulating layers, which are alternately stacked on the substrate in a vertical direction, and having a stepwise structure on the contact region; vertical structures penetrating the stacked structure in the cell array region, each of the vertical structures constituting a cell string; and word line contact plugs, each penetrating an uppermost electrode among the plurality of electrodes in a region of each of tread portions of the stacked structure having the stepwise structure, being connected to another electrode under the penetrated uppermost electrode, and being electrically insulated from the penetrated uppermost electrode.

Abstract: A three-dimensional semiconductor device includes: a substrate having a cell array region and a contact region; a stacked structure including a plurality of electrodes and a plurality of electrode isolation insulating layers, which are alternately stacked on the substrate in a vertical direction, and having a stepwise structure on the contact region; vertical structures penetrating the stacked structure in the cell array region, each of the vertical structures constituting a cell string; and word line contact plugs, each penetrating an uppermost electrode among the plurality of electrodes in a region of each of tread portions of the stacked structure having the stepwise structure, being connected to another electrode under the penetrated uppermost electrode, and being electrically insulated from the penetrated uppermost electrode.