Abstract: A vertical memory device includes gate electrodes spaced apart from each other in a first direction. Each of the gate electrodes extends in a second direction. Insulation patterns extend in the second direction between adjacent gate electrodes. A channel structure extends in the first direction. The channel structure extends through at least a portion of the gate electrode structure and at least a portion of the insulation pattern structure. The gate electrode structure includes at least one first gate electrode and a plurality of second gate electrodes sequentially stacked in the first direction on the substrate. Lower and upper surfaces of a first insulation pattern are bent away from the upper surface of the substrate along the first direction. A sidewall connecting the lower and upper surfaces of the first insulation pattern is slanted with respect to the upper surface of the substrate.

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

Abstract: A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate linesare spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

Abstract: In a NAND type nonvolatile memory device, a first insulating layer covers a common drain region formed in a string active region and a peripheral active region. A second insulating layer covers the first insulating layer. A bit line plug penetrates the first and second insulating layers and is connected to the common drain region. A peripheral lower plug penetrates the first insulating layer and is connected to the peripheral active region. A peripheral upper plug penetrates the second insulating layer and is stacked on the peripheral lower plug.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a dielectric layer utilizing a plasma, wherein the plasma comprises a porogen and substantially no oxidizing agent, and then applying energy to the dielectric layer, wherein the porogen disposed within the dielectric layer decomposes to form at least one pore.

Abstract: In a NAND type nonvolatile memory device, a first insulating layer covers a common drain region formed in a string active region and a peripheral active region. A second insulating layer covers the first insulating layer. A bit line plug penetrates the first and second insulating layers and is connected to the common drain region. A peripheral lower plug penetrates the first insulating layer and is connected to the peripheral active region. A peripheral upper plug penetrates the second insulating layer and is stacked on the peripheral lower plug.

Abstract: A method for sealing a porous dielectric layer atop a substrate, wherein the dielectric layer is patterned to form at least a trench and at least a via, comprises applying a first plasma to a surface of the dielectric layer to silanolize the surface, treating the surface of the dielectric layer with a silazane to form a monolayer of silane molecules on the surface, and applying a second plasma to the surface of the dielectric layer to induce a polymerization of at least a portion of the silane molecules. The polymerized silane molecules form a cross-linked matrix that builds over a substantial portion of the surface of the dielectric layer and seals at least some of the exposed pores.

Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a layer defining an exhaust vent. At an appropriate time, the underlying sacrificial material is decomposed and exhausted away through the exhaust vent. Residue from the exhausted sacrificial material accumulates at the vent location during exhaustion until the vent is substantially occluded. As a result, an air gap is created having desirable characteristics as a dielectric.

Abstract: Systems and techniques relating to etching vias in integrated circuit devices, in one implementation, include: providing a dielectric material and a conductive material, removing a first portion of the dielectric material to form a hole in the dielectric material, performing a tapering etch that removes a second portion of the dielectric material to form a via that touches down on the conductive material, and laterally expanding a bottom dimension of the via without a significant increase in a depth of the via. The technique can also include: providing a substrate with the dielectric material and the conductive material attached without an associated etch stop layer, removing the first portion at a high etch rate, controlling ion bombardment and plasma chemistry to form a sloped bottom of the via, and performing an intensive ion bombarding plasma etch, laterally expanding the via bottom.

Abstract: A thin hard mask is formed over a semiconductor substrate. The thin hard mask allows diffusion of a sacrificial material or pore-forming agent therethrough to form an underlying air gap or porous dielectric region. The thin hard mask may be a polymer or an initially porous material that may be later densified. The thin hard mask may be used to prevent etch steps used in forming an unlanded via from reaching layers below the hard mask.

Abstract: A method of patterning a porous dielectric material that includes an ash process to treat the porous dielectric material. The treated porous dielectric material allows for the formation of a substantially continuous barrier layer, which can inhibit diffusion of, for example, a conductive material into to the dielectric material. Other embodiments are described and claimed.

Abstract: A polymer dielectric material includes a sidewall passivating layer on the opposing sidewall surfaces of an opening in the dielectric layer for a via or trench. The sidewall passivating layer may be deposited on the sidewall surfaces, as well as the bottom surface of an opening having a first depth in the polymer dielectric layer. After the sidewall passivating layer is added, the depth of the opening may be increased to a second depth. The sidewall passivating layer provides a barrier to removal of the polymer dielectric from the sidewalls, preventing or reducing undercutting below a hard mask.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a dielectric layer utilizing a plasma, wherein the plasma comprises a porogen and substantially no oxidizing agent, and then applying energy to the dielectric layer, wherein the porogen disposed within the dielectric layer decomposes to form at least one pore.

Abstract: A polymer dielectric material includes a sidewall passivating layer on the opposing sidewall surfaces of an opening in the dielectric layer for a via or trench. The sidewall passivating layer may be deposited on the sidewall surfaces, as well as the bottom surface of an opening having a first depth in the polymer dielectric layer. After the sidewall passivating layer is added, the depth of the opening may be increased to a second depth. The sidewall passivating layer provides a barrier to removal of the polymer dielectric from the sidewalls, preventing or reducing undercutting below a hard mask.

Abstract: A method of patterning a porous dielectric material that includes an ash process to treat the porous dielectric material. The treated porous dielectric material allows for the formation of a substantially continuous barrier layer, which can inhibit diffusion of, for example, a conductive material into to the dielectric material. Other embodiments are described and claimed.

Abstract: An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.

Abstract: A method for sealing a porous dielectric layer atop a substrate, wherein the dielectric layer is patterned to form at least a trench and at least a via, comprises applying a first plasma to a surface of the dielectric layer to silanolize the surface, treating the surface of the dielectric layer with a silazane to form a monolayer of silane molecules on the surface, and applying a second plasma to the surface of the dielectric layer to induce a polymerization of at least a portion of the silane molecules. The polymerized silane molecules form a cross-linked matrix that builds over a substantial portion of the surface of the dielectric layer and seals at least some of the exposed pores.

Abstract: An etch stopless interconnect structure. According to embodiments of the present invention, a via opening is formed in an interlayer dielectric over a metal layer to expose a portion of the metal layer. The opening is then partially filled with a gap fill material. The opening is then filled with a sacrificial material wherein the sacrificial material is formed on the gap fill material. A trench is then formed in the interlayer dielectric including a portion of the opening filled with the sacrificial material. The sacrificial material is then removed from the opening. The trench and opening are then filled with a conductive film.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a dielectric layer utilizing a plasma, wherein the plasma comprises a porogen and substantially no oxidizing agent, and then applying energy to the dielectric layer, wherein the porogen disposed within the dielectric layer decomposes to form at least one pore.