Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a dielectric layer utilizing a plasma, wherein the plasma comprises a porogen and substantially no oxidizing agent, and then applying energy to the dielectric layer, wherein the porogen disposed within the dielectric layer decomposes to form at least one pore.

Abstract: Apparatus and methods of fabricating an interconnect having a recessed capping layer. An embodiment of the present invention relates to the fabrication of an interconnect for a microelectronic device which includes a recessed capping layer, which substantially eliminates topography issues present in the known devices and provides improved encapsulation of the interconnect to prevent electromigration of the conductive material thereof.

Abstract: Polymer aggregates in a photoresist layer may be dissolved or reduced in dimension by treatment with supercritical carbon dioxide. The supercritical carbon dioxide may be used before and/or after development of the photoresist. The SCCO2 treatment causes swelling of the photoresist and may allow polymer aggregates in the photoresist to be dissolved. Controlled release of the carbon dioxide de-swells the photoresist, resulting in reduced line edge roughness of openings in the photoresist and reduced resistance of metal lines formed in the openings.

Abstract: Systems and techniques relating to etching vias in integrated circuit devices, in one implementation, include: providing a dielectric material and a conductive material, removing a first portion of the dielectric material to form a hole in the dielectric material, performing a tapering etch that removes a second portion of the dielectric material to form a via that touches down on the conductive material, and laterally expanding a bottom dimension of the via without a significant increase in a depth of the via. The technique can also include: providing a substrate with the dielectric material and the conductive material attached without an associated etch stop layer, removing the first portion at a high etch rate, controlling ion bombardment and plasma chemistry to form a sloped bottom of the via, and performing an intensive ion bombarding plasma etch, laterally expanding the via bottom.

Abstract: A method of etching a semiconductor structure is described herein. The method includes providing a hard mask layer covering a substrate, the hard mask layer having a window to expose a portion of the substrate. Further, a portion of the opening in the substrate is etched generating a hard mask undercut. Then, the hard mask layer is trim-etched to remove the hard mask undercut. Next, the portion of the opening in the substrate is etched for a second time, generating a hard mask undercut for a second time. Trim-etching the hard mask followed by etching the portion of the opening in the substrate is continuously repeated until a predetermined depth of the opening in the substrate is achieved.

Abstract: An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.

Abstract: An embodiment of the present invention includes a method to form an air gap in a multi-layer structure. A dual damascene structure is formed on a substrate. The dual damascene structure has a metallization layer, a barrier layer, a sacrificial layer, and a hard mask layer. The sacrificial layer is made of a first sacrificial material having substantial thermal stability and decomposable by an electron beam. The sacrificial layer is removed by the electron beam to create the air gap between the barrier layer and the hard mask layer.

Abstract: An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.

Abstract: An ultraviolet sensitive material may be formed within a semiconductor structure covered with a suitable hard mask. At an appropriate time, the underlying ultraviolet sensitive material may be exposed to ultraviolet radiation, causing the material to exhaust through the overlying hard mask. As a result, an air gap may be created having desirable characteristics as a dielectric.

Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a layer defining an exhaust vent. At an appropriate time, the underlying sacrificial material is decomposed and exhausted away through the exhaust vent. Residue from the exhausted sacrificial material accumulates at the vent location during exhaustion until the vent is substantially occluded. As a result, an air gap is created having desirable characteristics as a dielectric.

Abstract: An embodiment of the present invention includes a method to form an air gap in a multi-layer structure. A dual damascene structure is formed on a substrate. The dual damascene structure has a metallization layer, a barrier layer, a sacrificial layer, and a hard mask layer. The sacrificial layer is made of a first sacrificial material having substantial thermal stability and decomposable by an electron beam. The sacrificial layer is removed by the electron beam to create the air gap between the barrier layer and the hard mask layer.

Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a layer defining an exhaust vent. At an appropriate time, the underlying sacrificial material is decomposed and exhausted away through the exhaust vent. Residue from the exhausted sacrificial material accumulates at the vent location during exhaustion until the vent is substantially occluded. As a result, an air gap is created having desirable characteristics as a dielectric.

Abstract: Polymer aggregates in a photoresist layer may be dissolved or reduced in dimension by treatment with supercritical carbon dioxide. The supercritical carbon dioxide may be used before and/or after development of the photoresist. The SCCO2 treatment causes swelling of the photoresist and may allow polymer aggregates in the photoresist to be dissolved. Controlled release of the carbon dioxide de-swells the photoresist, resulting in reduced line edge roughness of openings in the photoresist and reduced resistance of metal lines formed in the openings.

Abstract: A thin hard mask is formed over a semiconductor substrate. The thin hard mask allows diffusion of a sacrificial material or pore-forming agent therethrough to form an underlying air gap or porous dielectric region. The thin hard mask may be a polymer or an initially porous material that may be later densified. The thin hard mask may be used to prevent etch steps used in forming an unlanded via from reaching layers below the hard mask.

Abstract: A polymer dielectric material includes a sidewall passivating layer on the opposing sidewall surfaces of an opening in the dielectric layer for a via or trench. The sidewall passivating layer may be deposited on the sidewall surfaces, as well as the bottom surface of an opening having a first depth in the polymer dielectric layer. After the sidewall passivating layer is added, the depth of the opening may be increased to a second depth. The sidewall passivating layer provides a barrier to removal of the polymer dielectric from the sidewalls, preventing or reducing undercutting below a hard mask.

Abstract: A method for making a semiconductor device is described. That method includes forming a sacrificial layer on a substrate, then forming a layer of photoresist on the sacrificial layer. After the photoresist layer is patterned, to form a patterned photoresist layer that has a first opening, a first part of the sacrificial layer is removed to generate an etched sacrificial layer that has a tapered etch profile. A second part of the sacrificial layer is then removed to generate an etched sacrificial layer that has a second opening that is substantially smaller than the first opening.

Abstract: An ultraviolet sensitive material may be formed within a semiconductor structure covered with a suitable hard mask. At an appropriate time, the underlying ultraviolet sensitive material may be exposed to ultraviolet radiation, causing the material to exhaust through the overlying hard mask. As a result, an air gap may be created having desirable characteristics as a dielectric.

Abstract: A method for making a semiconductor device is described. That method includes forming a sacrificial layer on a substrate, then forming a layer of photoresist on the sacrificial layer. After the photoresist layer is patterned, to form a patterned photoresist layer that has a first opening, part of the sacrificial layer is removed to generate an etched sacrificial layer that has a second opening that is substantially smaller than the first opening.

Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a layer defining an exhaust vent. At an appropriate time, the underlying sacrificial material is decomposed and exhausted away through the exhaust vent. Residue from the exhausted sacrificial material accumulates at the vent location during exhaustion until the vent is substantially occluded. As a result, an air gap is created having desirable characteristics as a dielectric.

Abstract: An ultraviolet sensitive material may be formed within a semiconductor structure covered with a suitable hard mask. At an appropriate time, the underlying ultraviolet sensitive material may be exposed to ultraviolet radiation, causing the material to exhaust through the overlying hard mask. As a result, an air gap may be created having desirable characteristics as a dielectric.