Abstract: An extreme ultra violet (EUV) lithography apparatus includes a light source that generates an EUV light beam, a scanner that receives the light from a junction with the light source and directs the light to a reticle stage, and a debris catcher disposed on a EUV beam path between the light source and the scanner. The debris catcher includes a network membrane including a plurality of nano-fibers.

Abstract: Methods for removing haze defects from a photomask or reticle are disclosed. The photomask is placed into a chamber which includes a hydrogen atmosphere. The photomask is then exposed to radiation. The energy from the radiation, together with the hydrogen, causes decomposition of the haze defects. The methods can be practiced on-site and quickly, without the need for wet chemicals or the need to remove the pellicle before cleaning of the photomask. A device for conducting the methods is also disclosed herein.

Abstract: A photolithography exposure of a photoresist coating on a semiconductor wafer uses an optical projection system to form a latent image. The photolithography exposure further uses a mask with a set of multiple pattern focus (MPF) marks. Each MPF mark of includes features having different critical dimension (CD) sizes. The latent image is developed to form a developed photoresist pattern. Dimension sizes are measured of features of the developed photoresist pattern corresponding to the features of the MPF marks having different CD sizes. A spatial focus map of the photolithography exposure is constructed based on the measured dimension sizes. To determine the focal distance at an MPF mark, ratios or differences may be determined between the measured dimension sizes corresponding to the features of the MPF marks having different CD sizes, and the focal distance at the location of the MFP mark constructed based on the determined ratios or differences.

Abstract: A display apparatus with touch sensing and force sensing functions includes a display panel, a first touch device, a conductive layer and a dielectric layer. The first touch device includes multiple touch sensing pads. The conductive layer includes multiple force sensing pads electrically connected to each other, where the touch sensing pads separately overlap the corresponding force sensing pads in a vertical projection direction. The dielectric layer is disposed between the conductive layer and the first touch device. The touch sensing pads, the dielectric layer and the force sensing pads form a force sensing device.

Abstract: A dual-mode capacitive touch display panel includes first and second substrates, a display layer disposed between the first and second substrates, at least two first touch electrodes, at least two second touch electrodes, plural pressure sensing electrodes, and a shielding conductive layer. The first and second touch electrodes are disposed on the first substrate and overlap sub-pixels thereon. The first and second touch electrodes are respectively separated. The pressure sensing electrodes are disposed on the second substrate, and overlap the corresponding first or second touch electrodes in a vertical projection direction. The shielding conductive layer is disposed on the second substrate and includes plural openings, the pressure sensing electrodes overlap the corresponding openings, and the pressure sensing electrodes have a lower surface resistance than the shielding conductive layer does.

Abstract: A dual-mode capacitive touch display panel includes first and second substrates, a display layer disposed between the first and second substrates, at least two first touch electrodes, at least two second touch electrodes, plural pressure sensing electrodes, and a shielding conductive layer. The first and second touch electrodes are disposed on the first substrate and overlap sub-pixels thereon. The first and second touch electrodes are respectively separated. The pressure sensing electrodes are disposed on the second substrate, and overlap the corresponding first or second touch electrodes in a vertical projection direction. The shielding conductive layer is disposed on the second substrate and includes plural openings, the pressure sensing electrodes overlap the corresponding openings, and the pressure sensing electrodes have a lower surface resistance than the shielding conductive layer does.

Abstract: A dual-mode capacitive touch display panel includes first and second substrates, a display layer disposed between the first and second substrates, at least two first touch electrodes, at least two second touch electrodes, plural pressure sensing electrodes, and a shielding conductive layer. The first and second touch electrodes are disposed on the first substrate and overlap sub-pixels thereon. The first and second touch electrodes are respectively separated. The pressure sensing electrodes are disposed on the second substrate, and overlap the corresponding first or second touch electrodes in a vertical projection direction. The shielding conductive layer is disposed on the second substrate and includes plural openings, the pressure sensing electrodes overlap the corresponding openings, and the pressure sensing electrodes have a lower surface resistance than the shielding conductive layer does.

Abstract: A display apparatus with touch sensing and force sensing functions includes a display panel, a first touch device, a conductive layer and a dielectric layer. The first touch device includes multiple touch sensing pads. The conductive layer includes multiple force sensing pads electrically connected to each other, where the touch sensing pads separately overlap the corresponding force sensing pads in a vertical projection direction. The dielectric layer is disposed between the conductive layer and the first touch device. The touch sensing pads, the dielectric layer and the force sensing pads form a force sensing device.

Abstract: A dual-mode capacitive touch display panel includes first and second substrates, a display layer disposed between the first and second substrates, at least two first touch electrodes, at least two second touch electrodes, plural pressure sensing electrodes, and a shielding conductive layer. The first and second touch electrodes are disposed on the first substrate and overlap sub-pixels thereon. The first and second touch electrodes are respectively separated. The pressure sensing electrodes are disposed on the second substrate, and overlap the corresponding first or second touch electrodes in a vertical projection direction. The shielding conductive layer is disposed on the second substrate and includes plural openings, the pressure sensing electrodes overlap the corresponding openings, and the pressure sensing electrodes have a lower surface resistance than the shielding conductive layer does.

Abstract: A touch display panel and the driving method thereof are disclosed herein. The touch display panel comprises a plurality of first sensing electrodes, a plurality of second sensing electrodes, and a plurality of third sensing electrodes. The first sensing electrodes are configured to output a scanning signal. The second sensing electrodes are configured to generate a pressure detecting signal according to the scanning signal in a first period of a frame, and generate a touch detecting signal according to the scanning signal in a second period of the frame. The third sensing electrodes are arranged between the second sensing electrodes and configured to receive a predetermined voltage with a fixed level in the first period, and to be in a floating state in the second period.

Abstract: The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.

Abstract: A method including bonding a process wafer having integrated circuits and a carrier wafer having at least one alignment mark to form a wafer assembly. The method further includes aligning the wafer assembly using the at least one alignment mark of the carrier wafer.

Abstract: The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

Abstract: A method including bonding a process wafer having integrated circuits and a carrier wafer having at least one alignment mark to form a wafer assembly. The method further includes aligning the wafer assembly using the at least one alignment mark of the carrier wafer.

Abstract: A three-dimensional display including a display and a micro-lens is provided. The display has a plurality of pixel units thereon, and each pixel unit has a pixel pitch i. The micro-lens is disposed at a side of the display, the micro-lens has a plurality of lens units thereon, and each lens unit has a lens pitch l. A right eye viewing zone and a left eye viewing zone are formed if an image displayed from the display passes though the micro-lens, wherein a distance between the center of the right eye viewing zone and the center of the left eye viewing zone is wz, and lens pitch l satisfies: 2 ? i > l ? 2 ? i × w z w z + i , wz is between 70 and 500 mm and i is between 0.1 and 500 ?m.

Abstract: A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark.

Abstract: A display device including a liquid crystal lens and a display panel is provided. The liquid crystal lens is disposed above the display panel and includes a first substrate, a second substrate opposite to the first substrate, a liquid crystal layer between the first and the second substrates, driving electrodes located between the first substrate and the liquid crystal layer and arranged in a pitch, and an opposite electrode layer located between the second substrate and the liquid crystal layer. The display panel has display units arrange in the pitch. In a 3D display mode, two adjacent driving electrodes in the liquid crystal lens are respectively driven at a first time period and a second time period. The liquid crystal lens and the display panel are switched synchronically so that each display unit respectively displays images with different parallax at the first and the second time periods.

Abstract: The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

Abstract: A method and system to improve scanner throughput is provided. An image from a reticle is projected onto a substrate using a continuous linear scanning procedure in which an entire column of die or cells of die is scanned continuously, i.e. without stepping to a different location. Each scan includes translating a substrate with respect to a fixed beam. While the substrate is translated, the reticle is also translated. When a first die or cell of die is projected onto the substrate, the reticle translates along a direction opposite the scan direction and as the scan continues along the same direction, the reticle then translates in the opposite direction of the substrate thereby forming an inverted pattern on the next die or cell. The time associated with exposing the substrate is minimized as the stepping operation only occurs after a complete column of cells is scanned.

Abstract: The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.