Patents by Inventor I-Hsiung Huang
I-Hsiung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100013105Abstract: A method of manufacturing a photomask is described. The graphic data of the photomask are provided, and than an optical proximity correction is performed to the graphic data. A process rule check is then performed to the graphic data with the optical proximity correction. When at least one failed pattern not passing the process rule check is found in the graphic data, a repair procedure is performed only to the failed pattern so that the failed pattern can pass the process rule check. The patterns of the photomask are then formed according to the corrected and repaired graphic data.Type: ApplicationFiled: September 28, 2009Publication date: January 21, 2010Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ling-Chieh Lin, Chien-Fu Lee, I-Hsiung Huang
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Patent number: 7617475Abstract: A method of manufacturing a photomask is described. The graphic data of the photomask are provided, and than an optical proximity correction is performed to the graphic data. A process rule check is then performed to the graphic data with the optical proximity correction. When at least one failed pattern not passing the process rule check is found in the graphic data, a repair procedure is performed only to the failed pattern so that the failed pattern can pass the process rule check. The patterns of the photomask are then formed according to the corrected and repaired graphic data.Type: GrantFiled: November 13, 2006Date of Patent: November 10, 2009Assignee: United Microelectronics Corp.Inventors: Ling-Chieh Lin, Chien-Fu Lee, I-Hsiung Huang
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Publication number: 20090206057Abstract: A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Hsiung Huang, Chi-Lun Lu, Heng-Jen Lee, Sheng-Chi Chin, Yao-Ching Ku
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Publication number: 20080178140Abstract: A method for correcting a photomask pattern is disclosed. The correction method determines a layout condition according to the space and line width of a layout pattern. The layout condition is used to determine the type of optical proximity correction to be used for a layout pattern in order to generate a correction pattern, and the correction pattern is compared with a predetermined specification. Furthermore, a modified-rule optical proximity correction table is employed to correct the special layout pattern. Therefore, the fidelity correction may be easily implemented.Type: ApplicationFiled: January 18, 2007Publication date: July 24, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ling-Chieh Lin, Chuen-Huei Yang, Chien-Fu Lee, I-Hsiung Huang
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Publication number: 20080163892Abstract: A method of an in situ cleaning of an objective lens of a semiconductor apparatus includes placing a cleaning wafer having a detergent layer on a scanning stage of the semiconductor apparatus. A cleaning composition in the detergent layer is dissolved by using an immersion liquid (water), so that the cleaning composition reacts with the contaminants on the objective lens. Thereafter, the objective lens is rinsed with another solvent.Type: ApplicationFiled: January 8, 2007Publication date: July 10, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: I-Hsiung Huang, Ling-Chieh Lin
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Publication number: 20080113274Abstract: A method of manufacturing a photomask is described. The graphic data of the photomask are provided, and than an optical proximity correction is performed to the graphic data. A process rule check is then performed to the graphic data with the optical proximity correction. When at least one failed pattern not passing the process rule check is found in the graphic data, a repair procedure is performed only to the failed pattern so that the failed pattern can pass the process rule check. The patterns of the photomask are then formed according to the corrected and repaired graphic data.Type: ApplicationFiled: November 13, 2006Publication date: May 15, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: LING-CHIEH LIN, CHIEN-FU LEE, I-HSIUNG HUANG
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Publication number: 20070053077Abstract: A customer illumination aperture (CIA) structure for lithographic exposure is disclosed, including a central part and at least one off-axis part around the central part. The off-axis part of the CIA is disposed in a symmetric manner with respect to the central part.Type: ApplicationFiled: September 2, 2005Publication date: March 8, 2007Inventors: Ling-Chieh Lin, I-Hsiung Huang, Te-Hung Wu, Chin-Lung Lin
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Patent number: 6839126Abstract: A photolithography process with multiple exposures is provided. A photomask is placed and aligned above a wafer having a photoresist formed thereon at a predetermined distance. Multiple exposures are sequentially performed on the photoresist through the photomask. Each of the multiple exposures is provided with a respective illuminating setting that is optimized for one duty ratio of the photomask. Thereby, an optimum through-pitch performance for pattern transfer from the photomask unto the photoresist is obtained. Then, a development is performed on the photoresist.Type: GrantFiled: January 3, 2002Date of Patent: January 4, 2005Assignee: United Microelectronics Corp.Inventors: Yeong-Song Yen, I-Hsiung Huang, Jiunn-Ren Hwang, Kuei-Chun Hung, Ching-Hsu Chang
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Patent number: 6680163Abstract: A method of forming an opening in a wafer layer is described. At least two patterned photoresist layers are formed on a wafer layer. Each photoresist layer comprises patterns of various configurations. The photoresist layers are stacked to form an opening pattern that expose the underlying wafer layer by superpositioning the space between the patterns in the first photoresist layer and the space between the patterns in the second photoresist layer. The wafer layer exposed by the opening pattern is then etched to form an opening.Type: GrantFiled: December 23, 2002Date of Patent: January 20, 2004Assignee: United Microelectronics Corp.Inventors: Jiunn-Ren Hwang, I-Hsiung Huang
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Patent number: 6664028Abstract: A method of forming an opening in a wafer layer. At least two patterned photoresist layers are formed on a wafer layer. Using different photoresist layers, many openings are defined. The wafer layer is then etched to form the opening. Each photoresist layer has a parallel linear pattern such as parallel strips or an array of rectangular blocks. The photoresist layers are superposed in a way that spaces between the patterns for each photoresist layers overlapped with each other for form openings that expose the underlying wafer layers. The wafer layer exposed in the openings is then etched to form contact/via holes without rounded corners while the rounded profiles has been cancelled by the superposition of the photoresist layers.Type: GrantFiled: December 4, 2000Date of Patent: December 16, 2003Assignee: United Microelectronics Corp.Inventors: Jiunn-Ren Hwang, I-Hsiung Huang
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Patent number: 6656667Abstract: A multiple resist layer photolithographic process. A substrate having an insulation layer and a first photoresist layer sequentially stacked thereon is provided. A first light-exposure is conducted to transfer a pattern on a photomask to the first photoresist layer, thereby forming a first exposure pattern. A post-exposure baking is carried out and then the first photoresist layer is developed. A second photoresist layer is formed over the patterned first photoresist layer. A second photo-exposure is conducted to transfer the pattern on the same photomask to the second photoresist layer, thereby forming a second exposure pattern. The second exposure pattern and the first exposure pattern are aligned. Finally, the second photoresist layer is developed.Type: GrantFiled: April 13, 2001Date of Patent: December 2, 2003Assignee: United Microelectronics Corp.Inventors: I-Hsiung Huang, Jiunn-Ren Hwang
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Publication number: 20030129543Abstract: A method of forming an opening in a wafer layer is described. At least two patterned photoresist layers are formed on a wafer layer. Each photoresist layer comprises patterns of various configurations. The photoresist layers are stacked to form an opening pattern that expose the underlying wafer layer by superpositioning the space between the patterns in the first photoresist layer and the space between the patterns in the second photoresist layer. The wafer layer exposed by the opening pattern is then etched to form an opening.Type: ApplicationFiled: December 23, 2002Publication date: July 10, 2003Inventors: Jiunn-Ren Hwang, I-Hsiung Huang
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Patent number: 6589881Abstract: A method of forming a dual damascene structure. A substrate having a conductive layer thereon is provided. A passivation layer, a first dielectric layer, an etching stop layer, a second dielectric layer and cap layer serving as a base anti-reflection coating are sequentially formed over the substrate. The cap layer and the second dielectric layer are patterned to form a first opening that exposes a portion of the etching stop layer. A patterned negative photoresist layer having a second opening therein is formed above the cap layer. The cap layer exposed by the second opening and the second dielectric layer exposed by the first opening are removed. Thereafter, the second dielectric layer exposed by the second opening is removed to form a trench and the first dielectric layer exposed by the first opening is removed to form a via opening. The passivation layer exposed by via opening and then the negative photoresist layer is removed.Type: GrantFiled: November 27, 2001Date of Patent: July 8, 2003Assignee: United Microelectronics Corp.Inventors: I-Hsiung Huang, Jiunn-Ren Hwang, Kuei-Chun Hung, Ching-Hsu Chang
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Publication number: 20030123039Abstract: A photolithography process with multiple exposures is provided. A photomask is placed and aligned above a wafer having a photoresist formed thereon at a predetermined distance. Multiple exposures are sequentially performed on the photoresist through the photomask. Each of the multiple exposures is provided with a respective illuminating setting that is optimized for one duty ratio of the photomask. Thereby, an optimum through-pitch performance for pattern transfer from the photomask unto the photoresist is obtained. Then, a development is performed on the photoresist.Type: ApplicationFiled: January 3, 2002Publication date: July 3, 2003Inventors: Yeong-Song Yen, I-Hsiung Huang, Jiunn-Ren Hwang, Kuei-Chun Hung, Ching-Hsu Chang
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Patent number: 6582858Abstract: The present invention provides An alternating phase shifting mask (Alt-PSM), that is to be used in a double exposure lithographic process with a light source of 248 nm. The Alt-PSM comprises: (1) a quartz substrate; (2) at least one semi-dense line on the substrate, wherein the semi-dense line is adjacent to a clear region with a width larger than 2 nm on one side and on the other side is adjacent to a dense-line pattern with a narrow pitch; (3) a first phase shifting region, which is located between the dense line pattern and the semi-dense line pattern and is adjacent to the semi-dense line; and (4) a second phase shifting region with a predetermined width, which is adjacent to the semi-dense line and located on the side opposite to the first phase shifting region; wherein the phase difference between the first phase shifting region and the second phase shifting region is 180 degree.Type: GrantFiled: September 7, 2001Date of Patent: June 24, 2003Assignee: United Microelectronics Corp.Inventors: Chien-Wen Lai, Chien-Ming Wang, Feng-Yuan Chang, I-Hsiung Huang
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Patent number: 6579790Abstract: A method of fabricating a dual damascene opening in a dielectric layer above a substrate. A first photoresist layer having a first opening therein is formed over the dielectric layer. The first opening exposes the dielectric layer at a position where a via is desired. A buffer layer is formed over the first photoresist layer. A second photoresist layer having a second opening is formed over the buffer layer. The second opening exposes the area where a conductive wire is desired. The first opening and the second opening together form a metallic interconnect structure. Using the first and the second photoresist layer as a mask, a dual damascene structural opening that includes a via opening and a conductive wire trench is formed in the dielectric layer.Type: GrantFiled: November 6, 2000Date of Patent: June 17, 2003Assignee: United Microelectronics, Corp.Inventors: I-Hsiung Huang, Jiunn-Ren Hwang
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Publication number: 20030100188Abstract: A method of forming a dual damascene structure. A substrate has a conductive line formed thereon. A first dielectric layer, a second dielectric layer and cap layer serving as a base anti-reflection coating are sequentially formed over the substrate. The cap layer, the second dielectric layer and the first dielectric layer are patterned to form a via opening that exposes a portion of the conductive line. A patterned negative photoresist layer having a second opening therein is formed above the cap layer. Using the negative photoresist layer as a mask, the exposed cap layer and the second dielectric layer are removed to form a trench that exposes the first dielectric layer. The negative photoresist layer is removed. A conformal barrier layer and a conductive layer are sequentially formed over the trench and the via opening with the conductive layer completely filling the trench and the via opening.Type: ApplicationFiled: November 27, 2001Publication date: May 29, 2003Inventors: I-Hsiung Huang, Jiunn-Ren Hwang, Kuei-Chun Hung, Ching-Hsu Chang
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Publication number: 20030096496Abstract: A method of forming a dual damascene structure. A substrate has a conductive line thereon. A first dielectric layer, a second dielectric layer, a base anti-reflection coating and a spin-on dielectric layer are sequentially formed over the substrate. The spin-on dielectric layer, the base anti-reflection coating and the second dielectric layer are patterned to form an opening in the second dielectric layer and a first trench in the spin-on dielectric layer and the base anti-reflection coating. Using the spin-on dielectric layer and the base anti-reflection coating as a mask, the exposed first dielectric layer within the opening is removed to form a via opening that exposes a portion of the substrate. The exposed second dielectric layer within the first trench is also removed to form a second trench that exposes a portion of the first dielectric layer. Thereafter, the spin-on dielectric layer and the base anti-reflection coating are removed.Type: ApplicationFiled: November 20, 2001Publication date: May 22, 2003Inventors: I-Hsiung Huang, Jiunn-Ren Hwang, Kuei-Chun Hung, Yeong-Song Yen
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Patent number: 6541782Abstract: An electron beam photolithographic process for patterning an insulation layer over a substrate. A conductive photoresist layer having a conjugate structure is formed over the insulation layer. An electron beam photolithographic process is conducted using a photomask so that the pattern on the photomask is transferred to the conductive photoresist layer.Type: GrantFiled: December 5, 2000Date of Patent: April 1, 2003Assignee: United Microelectronics Copr.Inventors: I-Hsiung Huang, Jiunn-Ren Hwang
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Publication number: 20030051224Abstract: A method of modifying a photo mask pattern by using computer aided design (CAD) is described. The photo mask pattern is used to manufacture a photo mask for transferal to a photoresist layer formed on a surface of a semiconductor wafer so as to form a predetermined original pattern. A first modification is first performed according to an optic proximity effect, and then a second modification is performed according to a line end shortening effect. The present invention prevents the line end shortening effect from occurring in a subsequent trim down etching process of the original pattern performed for reducing its critical dimension.Type: ApplicationFiled: September 7, 2001Publication date: March 13, 2003Inventors: I-Hsiung Huang, Kuei-Shun Chen, Feng-Yuan Chang, Chien-Ming Wang