Abstract: The present invention provides An alternating phase shifting mask (Alt-PSM), that is to be used in a double exposure lithographic process with a light source of 248 nm. The Alt-PSM comprises: (1) a quartz substrate; (2) at least one semi-dense line on the substrate, wherein the semi-dense line is adjacent to a clear region with a width larger than 2 nm on one side and on the other side is adjacent to a dense-line pattern with a narrow pitch; (3) a first phase shifting region, which is located between the dense line pattern and the semi-dense line pattern and is adjacent to the semi-dense line; and (4) a second phase shifting region with a predetermined width, which is adjacent to the semi-dense line and located on the side opposite to the first phase shifting region; wherein the phase difference between the first phase shifting region and the second phase shifting region is 180 degree.

Abstract: This method comprising a stop layer, a dielectric layer, a bottom hard layer and top hard mask layer are formed on a substrate, sequentially. A via pattern photoresist layer is formed on the top hard mask layer. The top hard mask layer is etched by using the via pattern photoresist layer as a mask to transfer the via pattern into the top hard mask layer then removed the via pattern photoresist layer. A trench pattern photoresist layer is formed on the top hard mask layer wherein the trench pattern is over the via pattern. The bottom hard mask layer is etched by using the top hard mask layer as a mask to transfer the via pattern into the bottom hard mask layer. The top hard mask layer is etched by using the trench pattern photoresist layer as a mask, wherein the via pattern is transferred into a portion of the dielectric layer. The bottom hard mask layer is etched by using the top hard mask layer as a mask, wherein the via pattern is transferred into the dielectric layer.

Abstract: A process for increasing the line width window in a semiconductor process, which is suitable to be used to increase the line width widow at the time of the exposure of an iso-line pattern under 0.13 &mgr;m. This process includes: first forming a positive photoresist layer on the base, then using the first photomask to conduct the first exposure step on the positive photoresist layer. The first photomask is designed to have at least one main line that is opaque. On each of the two sides of the main line, there is a scattering bar. The width of the two scattering bars is greater than ⅓ of the wavelength of the light source that is used, and less than the width of the main line. The second photomask is used to conduct the second exposure step on the positive photoresist layer. The second photomask is designed to have at least two iso-lines that are pervious to light, and each of the two iso-lines is located at one of the two positions corresponding to the two scattering bars of the first photomask design.

Abstract: A thermal flow photolithographic process. A thermal flow photoresist is provided. A cross-linking agent is added to the thermal flow photoresist to form a high-temperature cross-linking photoresist material. A substrate having an insulation layer thereon is provided. The high-temperature cross-linking photoresist is deposited over the insulation layer. The cross-linked photoresist layer on the insulation layer is exposed to light, chemically developed and then heated to cause thermal flow.

Abstract: A dynamic random access memory (DRAM) is formed on a semiconductor wafer, the semiconductor wafer including a substrate, a thin film layer positioned on the substrate, and a photoresist layer positioned on the thin film layer. Two exposure processes are employed. The first exposure process forms first exposure regions that are linear and parallel with each other on the photoresist layer. The second exposure process forms second exposure regions that are interlaced with and perpendicular to each other on the photoresist layer. Performing a development process to the wafer removes the first exposure regions and the second exposure regions of the photoresist layer to form an array photoresist layer on the thin film layer. The array photoresist layer functions as a mask to perform an etching process to the thin film layer for forming an array thin film layer, the array thin film layer acting as a storage nodes in the DRAM.

Abstract: In accordance with the present invention, a method for forming a via-first dual damascene interconnect structure by using gap-filling material whose thickness is easily controlled by a developer is provided. The essential part of the present invention is the application of gap-filling materials such as novolak, PHS, acrylate, methacrylate, and COMA to fill vias. Filling vias with these materials can get a greater planar topography for trench patterning due to its excellent gap-filling capacity, protect the bottom of vias from damage during the trench etch, and prevent the fence problem by using a developer to control its thickness in vias.

Abstract: A multiple resist layer photolithographic process. A substrate having an insulation layer and a first photoresist layer sequentially stacked thereon is provided. A first light-exposure is conducted to transfer a pattern on a photomask to the first photoresist layer, thereby forming a first exposure pattern. A post-exposure baking is carried out and then the first photoresist layer is developed. A second photoresist layer is formed over the patterned first photoresist layer. A second photo-exposure is conducted to transfer the pattern on the same photomask to the second photoresist layer, thereby forming a second exposure pattern. The second exposure pattern and the first exposure pattern are aligned. Finally, the second photoresist layer is developed.

Abstract: A method of improving a photoresist profile. After a photoresist layer is developed, a hard bake is performed at a temperature lower than a glass transition temperature of the photoresist layer. The photoresist layer is thus able to reflow, so that the profile can be modified. Or alternatively, the hard bake step can be replace by first performing a hard bake at a temperature higher than the glass transition temperature, followed by performing a flow bake at a temperature lower than the glass transition temperature.

Abstract: A thermal flow photolithographic process. A thermal flow photoresist is provided. A cross-linking agent is added to the thermal flow photoresist to form a high-temperature cross-linking photoresist material. A substrate having an insulation layer thereon is provided. The high-temperature cross-linking photoresist is deposited over the insulation layer. The cross-linked photoresist layer on the insulation layer is exposed to light, chemically developed and then heated to cause thermal flow.

Abstract: A method of forming an opening in a wafer layer. At least two patterned photoresist layers are formed on a wafer layer. Using different photoresist layers, many openings are defined. The wafer layer is then etched to form the opening. Each photoresist layer has a parallel linear pattern such as parallel strips or an array of rectangular blocks. The photoresist layers are superposed in a way that spaces between the patterns for each photoresist layers overlapped with each other for form openings that expose the underlying wafer layers. The wafer layer exposed in the openings is then etched to form contact/via holes without rounded corners while the rounded profiles has been cancelled by the superposition of the photoresist layers.

Abstract: An electron beam photolithographic process for patterning an insulation layer over a substrate. A conductive photoresist layer having a conjugate structure is formed over the insulation layer. An electron beam photolithographic process is conducted using a photomask so that the pattern on the photomask is transferred to the conductive photoresist layer.

Abstract: A dual damascene process involves forming a first passivation layer, a first dielectric layer and a second passivation layer on a substrate of a semiconductor wafer. A first lithography and etching process is performed to form at least one via hole in the second passivation layer and the first dielectric layer. Thereafter, a second dielectric layer and a third passivation layer are formed on the surface of the semiconductor wafer followed by performing a second lithography and etching process to form at least one trench in the third passivation layer and the second dielectric layer. The trench and the via hole together construct a dual damascene structure. Finally, a barrier layer and a metal layer are formed on the surface of the semiconductor wafer, and a chemical-mechanical-polishing (CMP) process is performed to complete the dual damascene process.

Abstract: A method of forming a contact opening. A substrate having a conductive structure and a dielectric layer thereon is provided. A first photoresist layer is formed over the dielectric layer. A first photo-exposure followed by a photoresist development is conducted so that an opening pattern on the photomask is transferred to the first photoresist layer. The first photoresist layer includes a first opening that exposes a portion of the dielectric layer. A second photoresist layer is formed over the patterned first photoresist layer. The photomask is shifted horizontally relative to the substrate. A second photo-exposure followed by a photoresist development is conducted so that the opening pattern on the photomask is transferred to the second photoresist layer. The second photoresist layer includes a second opening that exposes a portion of the first photoresist layer and a portion of the first opening.

Abstract: A method is to form a dielectric layer with low dielectric constant on a hydrophilic dielectric layer. The method includes providing a substrate, which has a first dielectric layer on top. A hydrophilic second dielectric layer is formed on the first dielectric layer. A HMDS adhesion promoter layer is formed on the second dielectric layer. A dielectric layer with low dielectric constant, such as organic spin-on dielectric material or a hydrophilic dielectric material, is formed on the HMDS adhesion promoter layer. In the foregoing, the HMDS adhesion promoter layer has thickness of about 10-20 angstroms.

Abstract: A method of forming a multiple layer damascene structure. A substrate comprising of a multi-layered stack that includes, from bottom to top, a metallic layer, a first etching stop layer, a first dielectric layer, a second etching stop layer and a second dielectric layer is provided. A photoresist layer having large area openings and vias pattern is formed over the substrate. Large area openings and vias that expose a portion of the first etching stop layer are formed in the substrate. A barrier layer that fills all the large area openings and vias is formed over the substrate. Chemical-mechanical polishing is conducted to remove a portion of the barrier layer and expose the second dielectric layer. A second photoresist having a trench pattern thereon is formed over the substrate. Using the second photoresist as a mask, etching is conducted so that the second etching stop layer around the vias is exposed. Lastly, the barrier layer is removed.

Abstract: The present invention fabricates a dual damascene structure. A passivation layer, a first dielectric layer, a second passivation layer, a second dielectric layer, a third passivation layer and a third dielectric layer are formed on the surface of the semiconductor wafer followed by etching the third dielectric layer to form a pattern of an upper trench of the dual damascene structure. Then the third passivation layer and the second dielectric layer are etched down to the surface of the second passivation layer so as to form a pattern of a via hole of the dual damascene structure. Thereafter, the third passivation layer and the second passivation layer not covered by the third dielectric layer and the second dielectric layer are removed. The third dielectric layer and the second passivation layer are used as hard masks to remove the second dielectric layer and the first dielectric layer until the surface of the first passivation layer.

Abstract: A photolithographic process for preventing the rounding of the corners of a pattern. A silicon wafer is provided. A first photoresist layer is formed over the silicon wafer and then patterned to form a first group of mutually parallel photoresist lines along a first direction. A second photoresist layer is formed over the silicon wafer and then patterned to form a second group of mutually parallel photoresist lines along a second direction. The first direction and the second direction are on the same plane but mutually perpendicular.

Abstract: A three-phase phase shift mask. On a transparent substrate, a non-transparent pattern covering a portion of the transparent substrate is formed, while the other portion of the substrate is remained exposed. A proximity region around a comer of the non-transparent pattern is equally partitioned three phase-shift areas different from each other with a phase shift of 120°. The formation of these three phase-shift areas uses two etching steps to form a first and a second phase-shift areas, while a portion of the exposed substrate is etched twice as a third phase-shift area.

Abstract: An optical proximity correction method for rectifying pattern on negative photoresist. Line pattern of integrated circuit is divided into L-shape regions or T-shaped regions. The L-shaped or T-shaped regions are further dissected into rectangular patches. Area of each rectangular patch is suitably reduced and reproduced onto a photomask. The photomask is used to form a corrected photoresist pattern.