Patents by Inventor Ichiro Fujimori
Ichiro Fujimori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9189043Abstract: Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. The PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required. If the PSE finds the PD to be non-compatible, the PSE can prevent the application of power to that PD device, protecting the PD from possible damage.Type: GrantFiled: March 22, 2013Date of Patent: November 17, 2015Assignee: Broadcom CorporationInventors: Pieter Vorenkamp, Agnes Woo, Anil Tammineedi, Ichiro Fujimori, David Chin, John Perzow
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Patent number: 8886840Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fiber Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.Type: GrantFiled: June 21, 2013Date of Patent: November 11, 2014Assignee: Broadcom CorporationInventors: Ichiro Fujimori, Tuan Hoang, Ben Tan, Lorenzo Longo
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Patent number: 8866552Abstract: Disclosed are various embodiments of a current-mode line driver that may facilitate transmitting signals to a load. The current-mode line driver may comprise a common-mode current sense element that provides a signal corresponding to the common-mode output current of the line driver. A transconductance element receives the signal from the common-mode current sense element and provides a compensating current that is based at least in part on the signal. The compensating current may reduce the common-mode output current of the line driver.Type: GrantFiled: December 20, 2012Date of Patent: October 21, 2014Assignee: Broadcom CorporationInventors: Hui Pan, Yuan Yao, Mostafa Hammad, Karim Vincent Abdelhalim, Junhua Tan, Ichiro Fujimori
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Patent number: 8782442Abstract: An apparatus and method for multi-point detection in a power source equipment (PSE) device is provided. During multi-point detection, a series of at least four currents is sequentially applied to a link port of the PSE device. Each current is applied during a different measurement interval. A voltage measurement sample is obtained for each of the measurement intervals. A difference in voltage between alternating voltage samples is determined and used by a detection module to determine whether a valid power device is coupled to the link port of the PSE.Type: GrantFiled: April 5, 2010Date of Patent: July 15, 2014Assignee: Broadcom CorporationInventors: Agnes Woo, Anil Tammineedi, Ichiro Fujimori, David Chin, John Perzow
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Publication number: 20140167851Abstract: Disclosed are various embodiments of a current-mode line driver that may facilitate transmitting signals to a load. The current-mode line driver may comprise a common-mode current sense element that provides a signal corresponding to the common-mode output current of the line driver. A transconductance element receives the signal from the common-mode current sense element and provides a compensating current that is based at least in part on the signal. The compensating current may reduce the common-mode output current of the line driver.Type: ApplicationFiled: December 20, 2012Publication date: June 19, 2014Applicant: BROADCOM CORPORATIONInventors: Hui Pan, Yuan Yao, Mostafa Hammad, Karim Vincent Abdelhalim, Junhua Tan, Ichiro Fujimori
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Publication number: 20130279551Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.Type: ApplicationFiled: June 21, 2013Publication date: October 24, 2013Inventors: Ichiro Fujimori, Tuan Hoang, Ben Tan, Lorenzo Longo
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Patent number: 8473640Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fiber Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.Type: GrantFiled: June 6, 2012Date of Patent: June 25, 2013Assignee: Broadcom CorporationInventors: Ichiro Fujimori, Tuan Hoang, Ben Tan, Lorenzo Longo
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Patent number: 8432142Abstract: Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. In addition, the PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required.Type: GrantFiled: January 17, 2007Date of Patent: April 30, 2013Assignee: Broadcom CorporationInventors: Pieter Vorenkamp, Agnes Woo, Anil Tammineedi, Ichiro Fujimori, David Chin, John Perzow
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Publication number: 20120243587Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.Type: ApplicationFiled: June 6, 2012Publication date: September 27, 2012Applicant: BROADCOM CORPORATIONInventors: Ichiro Fujimori, Tuan Hoang, Ben Tan, Lorenzo Longo
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Patent number: 8230114Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.Type: GrantFiled: October 29, 2002Date of Patent: July 24, 2012Assignee: Broadcom CorporationInventors: Ichiro Fujimori, Tuan Hoang, Ben Tan, Lorenzo Longo
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Patent number: 8090047Abstract: Systems and methods for optimizing operation of a transceiver device are disclosed. The method may include parallel processing an input signal through a first path having a first frequency response and a second path having a second frequency response. The second frequency response may be higher than the first frequency response. Signals from the first and second paths may be combined, creating an output signal having a desired gain and frequency. The parallel processing may adjust a gain of at least one of the first path and the second path. The parallel processing may equalize at least one of the first frequency response and the second frequency response. The input signal may be from a 10 GBit Ethernet channel and/or a Fibre channel.Type: GrantFiled: June 8, 2010Date of Patent: January 3, 2012Assignee: Broadcom CorporationInventors: Ichiro Fujimori, Davide Tonietto
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Patent number: 7974337Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.Type: GrantFiled: October 27, 2009Date of Patent: July 5, 2011Assignee: Broadcom CorporationInventors: Afshin Momtaz, Mario Caresosa, David Kyong-Sik Chung, Davide Tonietto, Guangming Yin, Bruce Currivan, Thomas Kolze, Ichiro Fujimori
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Patent number: 7936546Abstract: Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. In addition, the PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required.Type: GrantFiled: April 30, 2007Date of Patent: May 3, 2011Assignee: Broadcom CorporationInventors: Pieter Vorenkamp, Agnes Woo, Anil Tammineedi, Ichiro Fujimori, David Chin, John Perzow
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Patent number: 7863871Abstract: Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. In addition, the PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required. The PSE controller also monitors for a Maintain Power Signature (MPS).Type: GrantFiled: April 30, 2007Date of Patent: January 4, 2011Assignee: Broadcom CorporationInventors: Pieter Vorenkamp, Agnes Woo, Anil Tammineedi, Ichiro Fujimori, David Chin, John Perzow
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Publication number: 20100295607Abstract: A system for reducing noise in a chip is disclosed and may include a substrate, a first well disposed on top of the substrate, a second well and a third well that are both disposed within the first well, a first transistor disposed in the second well, a positive potential of a voltage source connected to a body of the first transistor, and a second transistor disposed in the third well. The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor. A body of the first transistor may be resistively coupled to the second well. The system may include a noisy voltage source, where a body and a source of the second transistor are both coupled to the noisy voltage source.Type: ApplicationFiled: August 3, 2010Publication date: November 25, 2010Inventor: Ichiro Fujimori
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Publication number: 20100257381Abstract: An apparatus and method for multi-point detection in a power source equipment (PSE) device is provided. During multi-point detection, a series of at least four currents is sequentially applied to a link port of the PSE device. Each current is applied during a different measurement interval. A voltage measurement sample is obtained for each of the measurement intervals. A difference in voltage between alternating voltage samples is determined and used by a detection module to determine whether a valid power device is coupled to the link port of the PSE.Type: ApplicationFiled: April 5, 2010Publication date: October 7, 2010Applicant: BROADCOM CORPORATIONInventors: Agnes Woo, Anil Tammineedi, Ichiro Fujimori, David Chin, John Perzow
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Publication number: 20100246658Abstract: Systems and methods for optimizing operation of a transceiver device are disclosed. The method may include parallel processing an input signal through a first path having a first frequency response and a second path having a second frequency response. The second frequency response may be higher than the first frequency response. Signals from the first and second paths may be combined, creating an output signal having a desired gain and frequency. The parallel processing may adjust a gain of at least one of the first path and the second path. The parallel processing may equalize at least one of the first frequency response and the second frequency response. The input signal may be from a 10 GBit Ethernet channel and/or a Fibre channel.Type: ApplicationFiled: June 8, 2010Publication date: September 30, 2010Inventors: Ichiro Fujimori, Davide Tonietto
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Patent number: 7781841Abstract: Certain embodiments of the invention may be found in, for example, a system that reduces noise in a substrate of a chip and may comprise a substrate layer that is integrated within the chip. A transistor layer is integrated within the chip and is shielded from the substrate layer by a shielding layer. At least one transistor of a first transistor type couples the transistor layer to the shielding layer and a quiet voltage source may be coupled to the transistor of the first transistor type. At least one transistor of a second transistor type is coupled to the shielding layer. The transistor of the second transistor type may be a n-type transistor, which may be disposed within the transistor layer and the transistor of the second transistor type may be resistively coupled to the shielding layer.Type: GrantFiled: March 15, 2004Date of Patent: August 24, 2010Inventor: Ichiro Fujimori
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Patent number: 7733998Abstract: Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider (704) may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster (702) coupled to the signal divider (704) may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device (130). An equalizer (706) coupled to the signal divider (704) may be configured to equalize the equalization adjustment signal within the multimode PHY device (130). A summer (708) coupled to the equalizer (706) and signal adjuster (702) may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device (130) to create an output equalized signal (712) having a desired gain and/or frequency response.Type: GrantFiled: April 2, 2007Date of Patent: June 8, 2010Inventors: Ichiro Fujimori, Davide Tonietto
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Patent number: 7711967Abstract: An apparatus and method for multi-point detection in a power source equipment (PSE) device is provided. During multi-point detection, a series of at least four currents is sequentially applied to a link port of the PSE device. Each current is applied during a different measurement interval. A voltage measurement sample is obtained for each of the measurement intervals. A difference in voltage between alternating voltage samples is determined and used by a detection module to determine whether a valid power device is coupled to the link port of the PSE.Type: GrantFiled: January 17, 2007Date of Patent: May 4, 2010Assignee: Broadcom CorporationInventors: Agnes Woo, Anil Tammineedi, Ichiro Fujimori, David Chin, John Perzow