Abstract: A bit stream multiplexer includes an input ordering block, a plurality of multiplexers, an output ordering block, and a Pseudo Random Bit Stream (PRBS) function. The input ordering block is operates to receive a first plurality of transmit bit streams at a first bit rate, order the first plurality of transmit bit streams based upon a first order select signal, and produce a first plurality of ordered transmit bit streams at the first bit rate. The input ordering block may also deskew the first plurality of transmit bit streams. The plurality of multiplexers operate to receive the first plurality of ordered transmit bit streams at the first bit rate and produce an interface plurality of transmit bit streams at an interface bit rate. The output ordering block operates to order the interface plurality of transmit bit streams based upon an interface order select signal. The PRBS function produces a PRBS that is coupled to at least one of the interface plurality of transmit bit streams.

Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.

Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

Abstract: An apparatus and method are disclosed to aid a transceiver chip, in a wide-band serial data communications system, in receiving data at multiple data rates. A multi-rate filter within the transceiver chip is implemented as at least one adjustable-rate filter stage and a limiting stage. The at least one adjustable-rate filter stage is used to generate a filtered serial data signal from a received serial data signal. The limiter stage generates a full-swing serial data signal from the filtered serial data signal. A bandwidth of the at least one adjustable-rate filter stage is adjustable in order to receive serial data signals at multiple data rates. The bandwidth of the multi-rate filter within the transceiver chip is selectable by the user of the wide-band communication system.

Abstract: Apparatus and method are disclosed for constructing an eye pattern from a serial data signal within a receiver used in a serial data communication system. The receiver is used to receive the serial data signal and generates an internal clock signal from the serial data signal using, at least in part, a CDR circuit. Timing data corresponding to a current phase of the clock signal is also generated within the receiver using an interpolator circuit. The serial data signal is sampled by an ADC using the clock signal to generate sampled data. The sampled data and timing data are processed within the receiver by a data processor to generate the eye pattern. The resultant eye pattern may be analyzed within the receiver with respect to at least one characteristic of the eye pattern. At least one parameter of the receiver may be adjusted in response to the foregoing analysis.

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

Abstract: Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing a second layer doped with a second dopant. A first signaling component of the signaling layer may be coupled to the second layer and a second signaling component of the signaling layer may be coupled to the second layer. The second layer may be coupled to the first layer, and this reduces the signal disturbing noise in the electronic device. Shielding the first layer from the signaling layer may comprise disposing the second layer between the first layer and the signaling layer. Shielding the first layer from the signaling layer may comprise disposing a deep N-well between the first layer and the signaling layer.

Abstract: Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. In addition, the PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required. The PSE controller also monitors for a Maintain Power Signature (MPS).

Abstract: Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. In addition, the PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required.

Abstract: Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider (704) may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster (702) coupled to the signal divider (704) may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device (130). An equalizer (706) coupled to the signal divider (704) may be configured to equalize the equalization adjustment signal within the multimode PHY device (130). A summer (708) coupled to the equalizer (706) and signal adjuster (702) may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device (130) to create an output equalized signal (712) having a desired gain and/or frequency response.

Abstract: Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. In addition, the PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required.

Abstract: An apparatus and method for multi-point detection in a power source equipment (PSE) device is provided. During multi-point detection, a series of at least four currents is sequentially applied to a link port of the PSE device. Each current is applied during a different measurement interval. A voltage measurement sample is obtained for each of the measurement intervals. A difference in voltage between alternating voltage samples is determined and used by a detection module to determine whether a valid power device is coupled to the link port of the PSE.

Abstract: Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster coupled to the signal divider may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device. An equalizer coupled to the signal divider may be configured to equalize the equalization adjustment signal within the multimode PHY device. A summer coupled to the equalizer and signal adjuster may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device to create an output equalized signal having a desired gain and/or frequency response.

Abstract: A hierarchical parallel pipelined circuit includes a first stage with a plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A second stage includes a second plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A multi-frequency, multi-phase clock clocks the first and second stages, the multi-frequency, multi-phase clock providing a first clock having a first frequency having either a single or plurality of phases, and a second clock having a second frequency having a plurality of phases. A first phase of a plurality of phases is phase locked to the first phase of the first clock. The clock frequency multiplied by the number of parallel devices in each stage is the throughput of the circuit and is kept constant across the stages.

Abstract: A hierarchical parallel pipelined circuit includes a first stage with a plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A second stage includes a second plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A multi-frequency, multi-phase clock clocks the first and second stages, the multi-frequency, multi-phase clock providing a first clock having a first frequency having either a single or plurality of phases, and a second clock having a second frequency having a plurality of phases. A first phase of a plurality of phases is phase locked to the first phase of the first clock. The clock frequency multiplied by the number of parallel devices in each stage is the throughput of the circuit and is kept constant across the stages.

Abstract: Certain embodiments of the invention may be found in, for example, a system that reduces noise in a substrate of a chip and may comprise a substrate and a first well disposed on top of the substrate. The first well may be a deep well. Notwithstanding, a second well and a third are both disposed within the first well and a first transistor may be disposed in the second well. A quiet voltage source may be connected to a body of the first transistor and a second transistor may be disposed in the third well. The first transistor may be a PMOS transistor and the second transistor may be an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor and a body of the first transistor may be resistively coupled to the second well.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: Disclosed herein is a system adapted to reduce noise in a substrate of a chip. The chip may include a substrate having a first well disposed there atop. The first well may be a deep well. A second well and a third may also be disposed within the first well. A first transistor may be disposed in the second well. A quiet voltage source may be connected to a body of the first transistor. A second transistor may be disposed in the third well. The first transistor may be a PMOS transistor and the second transistor may be an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor. A body of the first transistor may be resistively coupled to the second well.

Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.