Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: A circuit, system, and method are provided for imparting improved randomness into the selection of components or elements of a data converter, such as a D/A converter. The elements are intended to be of equal value, however, regardless of whether they are or not. A circuit is used to randomly select subsets of elements according to a bi-directional selection technique in order to effectively rending the elements or components of equal value. Associated with each component is a switch, and a subset of the plurality of components are correspondingly switched in successive order progressing in a first direction and, subsequently, in successive order progressing in a second direction opposite the first direction. Connecting components in a first direction from left-to-right follows by selecting components in a second direction from right-to-left, and then again selecting components in the first direction from left-to-right, and so forth.

Abstract: An analog-to-digital converter is provided for converting an analog signal to a one-bit digital bit stream. The A/D converter uses a multi-bit analog delta-sigma modulator coupled to receive the analog input signal, and a one-bit digital delta-sigma modulator coupled to receive the digital output from the multi-bit analog delta-sigma modulator. The analog delta-sigma modulator uses a multi-bit quantizer having minimal quantization noise, and the digital delta-sigma modulator converts the multi-bit quantizer output into a single bit delta-sigma digital format compatible with digital audio systems which require a one-bit delta-sigma format. Thus, the present A/D converter uses the benefits of a multi-bit quantizer, yet can produce a one-bit, delta-sigma modulator output. In addition to linking with the one-bit delta-sigma modulator, the multi-bit quantizer output can be fed directly into a digital audio system which uses a multi-bit encoded delta-sigma or PCM format.

Abstract: A D/A converter for converting a given digital signal into an analog signal includes a plurality of capacitors (C1, C2 . . . , Ci) for storing an electric charge corresponding to a predetermined reference voltage (Vr+or Vr-). The reference voltage is selected depending on the digital signal during a period when a clock .phi.1 is at a high level. A switch selection (SUG1-SUGi, SB) is used to connect each of the plurality of capacitors between an input terminal and an output terminal of an operational amplifier 100 during a period when a clock +2 is at a high level.

Abstract: An integrated circuit is provided for sourcing a mirrored current into a high impedance output node. A load may be coupled to the output node, and the mirrored current may be derived proportional to or substantially equal to current forwarded from a reference current source. The integrated circuit, or current mirror, includes a pair of series-connected output transistors coupled between the output node and a reference terminal. One of the output transistors is dimensioned with a channel that is short enough to ensure the threshold voltage of that transistor is smaller than the threshold voltage of the other transistor having a longer channel. Thus, one transistor utilizes the benefits of high density integrated circuit manufacture and, more specifically, short channel effects arising from channel length less than, e.g., 1.0 microns.

Abstract: A D/A switched capacitor circuit, employed as part of a delta-sigma modulator, is provided. The modulator forms part of an A/D converter system, and the switched capacitor circuit is controlled by careful selection of clock phases. The clock phases, or more specifically four clock phases, are provided to ground both plates of switched capacitors within the D/A circuit subsequent to their discharge upon the integrator and prior to the next sampling period. Full discharge of shared capacitors to a ground voltage substantially eliminates any data dependent loading of integrator offset voltages upon the reference voltage supplies. Substantial reduction or elimination of data-dependent values prevents ac modulation of the referenced voltage supply and the imputed noise associated therewith.

Abstract: A modulator, in conjunction with a load circuit, is provided. The modulator forms part of an A/D converter system. The modulator includes a series of switched capacitors connected in a shared capacitor arrangement. The shared capacitors receive samples from an input signal and, depending upon the logic value fed into a D/A converter, the shared capacitor further receives a feedback reference voltage. The reference voltage is thereby coupled to the switched capacitor network, as well as to a load circuit which cancels data-dependent values modulated upon the reference voltage supply. The load circuit thereby serves to eliminate ac components within the reference voltage supply resulting from data dependent loading.

Abstract: An analog-to-digital converter is provided for converting an analog signal to a digital signal and for maintaining a linear gain relationship therebetween, regardless of the analog input signal full scale voltage. The analog-to-digital converter utilizes oversampling and delta-sigma techniques within a cascaded, multiple order circuit arrangement. A local feedback loop is coupled across the output and input nodes of at least one latter order integrator within the first stage and subsequent stage of the cascaded analog-to-digital converter. The local feedback loop monitors the output from the connected integrator and modifies that output through local feedback to ensure the input level of the second and subsequent stages is optimally maintained. Proper scaling of the latter stages ensures that quantization noise caused by the first stage is cancelled, and that any and all direct noise leakage from the first stage does not enter into the digital signal produced by the noise cancellation circuit.