Patents by Inventor Idan Alrod

Idan Alrod has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ERROR CORRECTION CODE PROCESSING AND DATA SHAPING
    Publication number: 20170269839
    Abstract: A device includes a memory and a controller including a data shaping engine. The data shaping engine is configured to apply a mapping to input data that includes one or more m-tuples of bits to generate transformed data. The transformed data includes one or more n-tuples of bits, and n is greater than m. A relationship of a gray coding of m-tuples to a gray coding of n-tuples is indicated by the mapping. The input data includes a first number of bit values that represent a particular logical state, and the transformed data includes a second number of bit values that represent the particular logical state, the second number of bit values being less than the first number of bit values.
    Type: Application
    Filed: March 17, 2016
    Publication date: September 21, 2017
    Inventors: Idan Alrod, Eran Sharon, Ariel Navon
  • TEMPERATURE VARIATION COMPENSATION
    Publication number: 20170255403
    Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.
    Type: Application
    Filed: May 27, 2016
    Publication date: September 7, 2017
    Inventors: ERAN SHARON, NIAN NILES YANG, IDAN ALROD, EVGENY MEKHANIK, MARK SHLICK, JOANNA LAI
  • MULTI-TYPE PARITY BIT GENERATION FOR ENCODING AND DECODING
    Publication number: 20170255512
    Abstract: A non-volatile memory system may be configured to generate a codeword with first-type parity bits and one or more second-type parity bits. If a storage location in which the codeword is to be stored includes one or more bad memory cells, the bit sequence of the codeword may be arranged so that at least some of the second-type parity bits are stored in the bad memory cells. During decoding, a first set of syndrome values may be determined for a first set of check nodes and a second set of syndrome values may be determined for a second set of check nodes. In some examples, a syndrome weight used for determining if convergence is achieved may be calculated using check nodes that are unassociated with the second-type parity bits.
    Type: Application
    Filed: August 31, 2016
    Publication date: September 7, 2017
    Applicant: SanDisk Technologies LLC
    Inventors: Ran Zamir, Alexander Bazarsky, Eran Sharon, Idan Alrod
  • ECC DECODING USING RAID-TYPE PARITY
    Publication number: 20170255518
    Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The data structure further includes stripe parity corresponding to portions of the codewords encoded according to a stripe correction scheme. The controller is configured, in response to the number of the undecodable codewords exceeding an erasure correction capacity of the stripe correction scheme, to provide information from a stripe decoding operation to an input of a ECC decoding operation corresponding to an undecodable codeword.
    Type: Application
    Filed: June 9, 2016
    Publication date: September 7, 2017
    Inventors: STELLA ACHTENBERG, ERAN SHARON, IDAN ALROD
  • ECC AND RAID-TYPE DECODING
    Publication number: 20170255517
    Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The controller includes a stripe generator and a stripe decoder. The stripe generator is configured, in response to the number of undecodable codewords exceeding an erasure correction capacity of a stripe correction scheme, to generate trial data for a stripe of the data structure, the trial data including at least one element that corresponds to erased data and at least another element that is associated with an undecodable codeword and that corresponds to valid data of the stripe. The stripe decoder is configured to initiate a stripe decode operation of the trial data.
    Type: Application
    Filed: June 9, 2016
    Publication date: September 7, 2017
    Inventors: STELLA ACHTENBERG, ERAN SHARON, IDAN ALROD
  • NON-VOLATILE MEMORY WITH CORRUPTION RECOVERY
    Publication number: 20170249207
    Abstract: A non-volatile storage system is provided that includes a mechanism to restore data that has been corrupted beyond the limits of traditional error correction. The system creates first level parity information for each subset of data to form multiple sets of programmable data, with each set of programmable data including a subset of data and corresponding first level parity. Separate second level parity is created for each set of programmable data. The system creates combined second level parity information based on a function of separate second level parity information for the multiple sets of programmable data. If a set of programmable data is found to be corrupt, the corrupt subset of data is recovered using the corrupt subset of data read from the non-volatile storage system, the corresponding first level parity read from the non-volatile storage system and the combined second level parity information.
    Type: Application
    Filed: February 29, 2016
    Publication date: August 31, 2017
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Eran Sharon, Idan Alrod
  • Data encoding techniques for a device
    Patent number: 9734009
    Abstract: A data storage device includes a controller and a non-volatile memory coupled to the controller. The controller is configured to generate first parity information based on first data and to generate second parity information based on second data. The non-volatile memory is configured to store the first data and the second data. The data storage device also includes a buffer configured to store the first parity information. The controller is further configured to generate joint parity information associated with the first data and the second data in response to a combined data size of the first data and the second data satisfying a threshold.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: August 15, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xinde Hu, Christopher John Petti, Eran Sharon, Idan Alrod, Ariel Navon
  • Disturb condition detection for a resistive random access memory
    Patent number: 9734903
    Abstract: A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed information in response to determining to access the second portion. The method further includes initiating a third operation to rewrite the information at the ReRAM in response to detecting an indication of a disturb condition based on the sensed information.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: August 15, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Ran Zamir, Eran Sharon, Idan Alrod, Ariel Navon, Tz-Yi Liu, Tianhong Yan
  • Data Recovery in Three Dimensional Non-Volatile Memory Array After Word Line Short
    Publication number: 20170228299
    Abstract: Data is programmed in a respective block of non-volatile three dimensional memory. The block contains a plurality of rows of subblocks, each row having S subblocks. Programming data in the respective block includes successively programming data in individual rows of the respective block. Programming data in each row is completed prior to programming data in a next row. Programming data in a row includes successively programming data in individual subblocks of the row, in a predefined order. The programming of data in each subblock is completed prior to programming data in a next subblock. While programming data in each individual subblock, a number of XOR signatures, sufficient in number to enable recovery from a short circuit that disables two or three word lines, are generated in volatile memory, and then copied to non-volatile memory prior to programming data in a next subblock in the respective block.
    Type: Application
    Filed: January 24, 2017
    Publication date: August 10, 2017
    Inventors: Ofer Shapira, Idan Alrod, Eran Sharon
  • Method and device for iteratively updating read voltages
    Patent number: 9728263
    Abstract: A data storage device includes a memory and a controller. Read voltages are updated based on adjusting a first read voltage without adjusting a second read voltage to generate multiple sets of read voltages, and the multiple sets of read voltages are used to generate multiple representations of data. A value of the first read voltages is selected based on error correction coding (ECC) related information related to the multiple representations of the data. In another embodiment, storage elements of the memory are sensed using a set of candidate read voltages to generate sensing data that is transferred to a memory accessible to the controller. The multiple representations of data may be generated based on the sensing data to emulate results of reading the storage elements using a different combination of candidate reading voltages.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: August 8, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Eran Sharon, Evgeny Mekhanik, Idan Alrod
  • Error correction based on historical bit error data
    Patent number: 9710329
    Abstract: A data storage device includes a memory including a plurality of storage elements. The data storage device further includes a controller coupled to the memory. The controller includes an error correction code (ECC) engine. The controller further includes a reliability engine configured to access historical bit error data. The historical bit error data includes a first count of bit errors associated with a first set of storage elements of the plurality of storage elements. The reliability engine is configured to generate reliability information based on the historical bit error data and to provide the reliability information to the ECC engine.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: July 18, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ronen Golan, Idan Alrod, Eli Elmoalem
  • Self-detecting a heating event to non-volatile storage
    Patent number: 9704595
    Abstract: Techniques are provided for non-volatile storage self-detecting that a heating event has occurred to the non-volatile storage. One example of the heating event is an Infrared (IR) reflow process. In one aspect, a block of memory cells in a memory device are put through a number of program/erase cycles. A group of the memory cells in the cycled block are programmed to a reference threshold voltage distribution. Some time may pass after programming the cycled block. The memory device self-detects that there has been a heating event in response to a shift in the reference VT distribution being more than an allowed amount. The memory device may switch from a first programming mode to a second programming mode in response to detecting that the heating event has occurred.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 11, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Alon Eyal, Idan Alrod, Eran Sharon, Ishai Ilani, Mark Murin, David Rozman, Wei-Cheng Lien, Deepanshu Dutta, Changyuan Chen
  • ERROR LOCATOR POLYNOMIAL DECODER AND METHOD
    Publication number: 20170187391
    Abstract: A decoder includes an error locator polynomial generator circuit configured to determine, during a first cycle of a clock signal, a first value of a parameter. The first value of the parameter is associated with a first iteration of a decode operation and is based on a value of an error locator polynomial associated with a prior iteration of the decode operation. The error locator polynomial generator circuit is further configured to determine, during a second cycle of the clock signal that sequentially follows the first cycle or during a third cycle of the clock signal that sequentially follows the second cycle, an adjusted value of the error locator polynomial. The adjusted value of the error locator polynomial is associated with a second iteration of the decode operation and is based on the first value of the parameter.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Inventors: ISHAI ILANI, IDAN ALROD
  • Rewritable Multibit Non-Volatile Memory With Soft Decode Optimization
    Publication number: 20170185299
    Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.
    Type: Application
    Filed: March 15, 2017
    Publication date: June 29, 2017
    Applicant: SanDisk Technologies LLC
    Inventors: Kevin Michael Conley, Raul-Adrian Cernea, Eran Sharon, Idan Alrod
  • PARTIAL SOFT BIT READ
    Publication number: 20170123902
    Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an error correction coding (ECC) decoder. The non-volatile memory is configured to sense hard bit data and soft bit data corresponding to multiple ECC codewords from a word line of the non-volatile memory and to sense soft bit data for the multiple ECC codewords. The soft bit data includes sub codes for each of the multiple ECC codewords. The non-volatile memory is configured to send less than all of the sensed soft bit sub codes to the ECC decoder.
    Type: Application
    Filed: October 29, 2015
    Publication date: May 4, 2017
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Abhijeet Manohar, Idan Alrod
  • SYSTEM AND METHOD OF DATA COMPRESSION
    Publication number: 20170123662
    Abstract: A data storage device includes a shaping engine and a compression engine. The shaping engine is configured to shape first data to generate second data. The compression engine is configured to compress the second data to generate third data.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: ERAN SHARON, ISHAI ILANI, IDAN ALROD, ARIEL NAVON, RAMI ROM
  • System and method of processing of duplicate data at a data storage device
    Patent number: 9639461
    Abstract: A data storage device includes a memory and a controller. A method may be performed at the data storage device. The method includes receiving a request to write data, generating a signature of the data, and searching a signature table to determine if the generated signature is in the signature table. The signature table includes at least one signature table entry that includes a signature of stored data and a physical address of the stored data.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 2, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yarden Eitan, Udi Agami, Eran Sharon, Idan Alrod
  • Rewritable multibit non-volatile memory with soft decode optimization
    Patent number: 9640253
    Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 2, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Kevin Michael Conley, Raul-Adrian Cernea, Eran Sharon, Idan Alrod
  • System and method of using multiple read operations
    Patent number: 9640270
    Abstract: Systems and methods are described for reading a storage element of a memory. In a particular embodiment, a method, in a data storage device including a controller and a non-volatile memory, where the non-volatile memory includes a plurality of storage elements, includes performing multiple read operations at a storage element of the non-volatile memory. Each read operation of the multiple read operations is performed using the same reading voltage. The method further includes determining a read value of the storage element based on the multiple read operations.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: May 2, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Idan Alrod, Eran Sharon
  • SYSTEMS AND METHODS OF DETECTING ERRORS DURING READ OPERATIONS AND SKIPPING WORD LINE PORTIONS
    Publication number: 20170116070
    Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The non-volatile memory includes a plurality of blocks and each block of the plurality of blocks includes a plurality of word lines. The controller is configured to receive data read from a word line of a block of the non-volatile memory and to determine an error indicator value based on the data. The controller is further configured to, responsive to the error indicator value satisfying a threshold, indicate that at least a portion of the word line is to be skipped during writing of second data to the block of the non-volatile memory.
    Type: Application
    Filed: October 22, 2015
    Publication date: April 27, 2017
    Inventors: IDAN ALROD, ERAN SHARON, YIGAL ELI, ROI KIRSHENBAUM, URI PELTZ, KARIN INBAR