Patents by Inventor Idan Alrod

Idan Alrod has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Storage device operations based on bit error rate (BER) estimate
    Patent number: 10180874
    Abstract: A data storage device may include a memory and a controller that includes an error correction coding (ECC) decoder configured to operate in a plurality of decoding modes. The controller also includes a bit error rate estimator configured to determine, based on data received from the memory, bit error rate estimates for ECC codewords from the memory. The controller also includes a data path management unit configured to reorder the codewords based on the bit error rate estimates and to provide the reordered codewords to the ECC decoder.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 15, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Alexander Bazarsky, Eran Sharon, Yuri Ryabinin, Yan Dumchin, Idan Alrod, Ariel Navon
  • Data recovery in three dimensional non-volatile memory array after word line short
    Patent number: 10133645
    Abstract: Data is programmed in a respective block of non-volatile three dimensional memory. The block contains a plurality of rows of subblocks, each row having S subblocks. Programming data in the respective block includes successively programming data in individual rows of the respective block. Programming data in each row is completed prior to programming data in a next row. Programming data in a row includes successively programming data in individual subblocks of the row, in a predefined order. The programming of data in each subblock is completed prior to programming data in a next subblock. While programming data in each individual subblock, a number of XOR signatures, sufficient in number to enable recovery from a short circuit that disables two or three word lines, are generated in volatile memory, and then copied to non-volatile memory prior to programming data in a next subblock in the respective block.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: November 20, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Ofer Shapira, Idan Alrod, Eran Sharon
  • STORAGE SYSTEM AND METHOD FOR BAD BLOCK RECYCLING
    Publication number: 20180315487
    Abstract: A storage system is provided comprising a controller and a memory. The controller is configured to identify at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline; identify which wordlines in the at least two physical blocks of memory are defective; and create a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory.
    Type: Application
    Filed: May 1, 2017
    Publication date: November 1, 2018
    Applicant: Western Digital Technologies, Inc.
    Inventors: DUDY Avraham, Ran Zamir, Idan Alrod, Eran Sharon
  • Error correction code processing and data shaping for reducing wear to a memory
    Patent number: 10114549
    Abstract: A device includes a memory and a controller including a data shaping engine. The data shaping engine is configured to apply a mapping to input data that includes one or more m-tuples of bits to generate transformed data. The transformed data includes one or more n-tuples of bits, and n is greater than m. A relationship of a gray coding of m-tuples to a gray coding of n-tuples is indicated by the mapping. The input data includes a first number of bit values that represent a particular logical state, and the transformed data includes a second number of bit values that represent the particular logical state, the second number of bit values being less than the first number of bit values.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Idan Alrod, Eran Sharon, Ariel Navon
  • Column-layered message-passing LDPC decoder
    Patent number: 10110249
    Abstract: In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: October 23, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Xinmiao Zhang, Alexander Bazarsky, Ran Zamir, Eran Sharon, Idan Alrod, Omer Fainzilber, Sanel Alterman
  • TEMPERATURE VARIATION COMPENSATION
    Publication number: 20180293029
    Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is operable to measure a first threshold voltage (Vt) of a memory cell under a first parameter at a read temperature and measure a second Vt of the memory cell under a second parameter at the read temperature in which the first parameter is different from the second parameter. A Vt correction term for the memory cell is determined based upon the first Vt measurement and the second Vt measurement. A read Vt of the memory cell is adjusted by using the Vt correction term.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Inventors: Stella Achtenberg, Eran Sharon, David Rozman, Alon Eyal, Idan Alrod, Dana Lee
  • TEMPERATURE VARIATION COMPENSATION
    Publication number: 20180293009
    Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.
    Type: Application
    Filed: June 7, 2018
    Publication date: October 11, 2018
    Inventors: Eran SHARON, Nian Niles YANG, Idan ALROD, Evgeny MEKHANIK, Mark SHLICK, Joanna LAI
  • Error locator polynomial decoder method
    Patent number: 10097208
    Abstract: A decoder includes an error locator polynomial generator circuit configured to determine, during a first cycle of a clock signal, a first value of a parameter. The first value of the parameter is associated with a first iteration of a decode operation and is based on a value of an error locator polynomial associated with a prior iteration of the decode operation. The error locator polynomial generator circuit is further configured to determine, during a second cycle of the clock signal that sequentially follows the first cycle or during a third cycle of the clock signal that sequentially follows the second cycle, an adjusted value of the error locator polynomial. The adjusted value of the error locator polynomial is associated with a second iteration of the decode operation and is based on the first value of the parameter.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: October 9, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ishai Ilani, Idan Alrod
  • USE OF MULTIPLE CODEBOOKS FOR PROGRAMMING DATA IN DIFFERENT MEMORY AREAS OF A STORAGE DEVICE
    Publication number: 20180287634
    Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Rami Rom, Idan Goldenberg, Alexander Bazarsky, Eran Sharon, Ran Zamir, Idan Alrod, Stella Achtenberg
  • MEMORY HEALTH MONITORING
    Publication number: 20180285018
    Abstract: A data storage device may be configured to write first data to a first set of storage elements of a non-volatile memory and to write second data to a second set of storage elements of the non-volatile memory. The first data may be processed by a data shaping operation, and the second data may not be processed by the data shaping operation. The data storage device may be further configured to read a representation of the second data from the second set of storage cells and to determine a block health metric of a portion of the non-volatile memory based on the representation of the second data. The portion may include the first set of storage elements and the second set of storage elements. As an illustrative, non-limiting example, the first portion may be a first block of the non-volatile memory.
    Type: Application
    Filed: June 7, 2018
    Publication date: October 4, 2018
    Inventors: Nian Niles YANG, Idan ALROD
  • Multi-stage decoder
    Patent number: 10089177
    Abstract: An apparatus includes a memory die including a group of storage elements and one or more unallocated redundant columns. A number of the unallocated redundant columns is based on a number of one or more bad columns of the memory die. The apparatus further includes a controller coupled to the memory. The controller is configured to receive data and redundancy information associated with the data from the memory. The data includes a first bit, and the redundancy information includes a second bit. The redundancy information is sensed from the one or more unallocated redundant columns and has a size that is based on the number of one or more bad columns. The controller is further configured to determine a value of the first bit based on one or more parity check conditions associated with the second bit.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 2, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Alexander Bazarsky, Ran Zamir, Eran Sharon, Idan Alrod
  • Word line defect detection and handling for a data storage device
    Patent number: 10083069
    Abstract: A data storage device includes a non-volatile memory and a controller. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: September 25, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Seungjune Jeon, Idan Alrod, Eran Sharon, Dana Lee
  • Shaped data associated with an erase operation
    Patent number: 10074427
    Abstract: A method includes, in a data storage device including a resistive memory, receiving, from an external device, an erase command to erase a portion of the resistive memory. The method further includes storing shaped data at the portion of the resistive memory responsive to the erase command. Shaped data is configured to control an amount of leakage current during a read and/or write operation at one or more storage elements that are adjacent to at least one storage element of the portion of the resistive memory.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: September 11, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Idan Alrod, Noam Presman, Ariel Navon, Tz-Yi Liu, Tianhong Yan
  • FIRST READ COUNTERMEASURES IN MEMORY
    Publication number: 20180254090
    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.
    Type: Application
    Filed: November 17, 2017
    Publication date: September 6, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Deepanshu Dutta, Idan Alrod, Huai-Yuan Tseng, Amul Desai, Jun Wan, Ken Cheah, Sarath Puthenthermadam
  • Head mountable camera system
    Patent number: 10061349
    Abstract: Head mountable camera devices, systems, and methods are disclosed.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: August 28, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Itzhak Pomerantz, Menahem Lasser, Rahav Yairi, Idan Alrod, Eran Sharon, Noam Presman, Ariel Navon
  • FIRST READ SOLUTION FOR MEMORY
    Publication number: 20180203763
    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.
    Type: Application
    Filed: March 14, 2018
    Publication date: July 19, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Idan Alrod, Eran Sharon, Alon Eyal, Liang Pang, Evgeny Mekhanik
  • FIRST READ SOLUTION FOR MEMORY
    Publication number: 20180203762
    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.
    Type: Application
    Filed: March 14, 2018
    Publication date: July 19, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Idan Alrod, Eran Sharon, Alon Eyal, Liang Pang, Evgeny Mekhanik
  • First read countermeasures in memory
    Patent number: 10026486
    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: July 17, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Deepanshu Dutta, Idan Alrod, Huai-Yuan Tseng, Amul Desai, Jun Wan, Ken Cheah, Sarath Puthenthermadam
  • Preliminary ready indication for memory operations on non-volatile memory
    Patent number: 10002649
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for providing a preliminary ready indication for non-volatile memory. A non-volatile memory element initiates a write operation for one or more storage cells of the non-volatile memory element. The non-volatile memory element determines whether a progress threshold is satisfied for the write operation. The non-volatile memory element provides a preliminary ready indication, indicating that the progress threshold is satisfied.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: June 19, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ronen Golan, Roie Shpaizman, Alex Bazarsky, Eli Elmoalem, Grishma Shah, Idan Alrod
  • Systems and methods of detecting errors during read operations and skipping word line portions
    Patent number: 10002042
    Abstract: A device includes a non-volatile memory and a controller coupled to the non-volatile memory. The non-volatile memory includes a plurality of blocks and each block of the plurality of blocks includes a plurality of word lines. The controller is configured to receive data read from a word line of a block of the non-volatile memory and to determine an error indicator value based on the data. The controller is further configured to, responsive to the error indicator value satisfying a threshold, indicate that at least a portion of the word line is to be skipped during writing of second data to the block of the non-volatile memory.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: June 19, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Idan Alrod, Eran Sharon, Yigal Eli, Roi Kirshenbaum, Uri Peltz, Karin Inbar