Patents by Inventor Idan Alrod

Idan Alrod has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Temperature variation compensation
    Patent number: 9996281
    Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: June 12, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Eran Sharon, Nian Niles Yang, Idan Alrod, Evgeny Mekhanik, Mark Shlick, Joanna Lai
  • ECC DECODER WITH MULTIPLE DECODING MODES
    Publication number: 20180159553
    Abstract: A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.
    Type: Application
    Filed: December 1, 2016
    Publication date: June 7, 2018
    Inventors: ERAN SHARON, IDAN GOLDENBERG, ISHAI ILANI, IDAN ALROD, YURI RYABININ, YAN DUMCHIN, MARK FITERMAN, RAN ZAMIR
  • Partial soft bit read
    Patent number: 9978462
    Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an error correction coding (ECC) decoder. The non-volatile memory is configured to sense hard bit data and soft bit data corresponding to multiple ECC codewords from a word line of the non-volatile memory and to sense soft bit data for the multiple ECC codewords. The soft bit data includes sub codes for each of the multiple ECC codewords. The non-volatile memory is configured to send less than all of the sensed soft bit sub codes to the ECC decoder.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 22, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Abhijeet Manohar, Idan Alrod
  • ECC and RAID-type decoding
    Patent number: 9959168
    Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The controller includes a stripe generator and a stripe decoder. The stripe generator is configured, in response to the number of undecodable codewords exceeding an erasure correction capacity of a stripe correction scheme, to generate trial data for a stripe of the data structure, the trial data including at least one element that corresponds to erased data and at least another element that is associated with an undecodable codeword and that corresponds to valid data of the stripe. The stripe decoder is configured to initiate a stripe decode operation of the trial data.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: May 1, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Stella Achtenberg, Eran Sharon, Idan Alrod
  • Command Sequence For First Read Solution For Memory
    Publication number: 20180114580
    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A command is issued for performing a conditioning operation which helps to transition the memory cells so that their threshold voltages are at predictable levels. In one approach, the conditioning operation is performed by applying a voltage pulse to one or more word lines in response to a trigger, such as detecting that a duration since a last sensing operation exceeds a threshold, detecting that a duration since a last performance of the conditioning operation exceeds a threshold, or a detecting that a read command has been issued. Moreover, the peak power consumption required to perform the conditioning operation can be reduced for various configurations of a memory device on one or more die.
    Type: Application
    Filed: February 23, 2017
    Publication date: April 26, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Idan Alrod, Eran Sharon, Alon Eyal, Liang Pang, Evgeny Mekhanik
  • First Read Solution For Memory
    Publication number: 20180113759
    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.
    Type: Application
    Filed: October 25, 2016
    Publication date: April 26, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Idan Alrod, Eran Sharon, Alon Eyal, Liang Pang, Evgeny Mekhanik
  • First read solution for memory
    Patent number: 9952944
    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: April 24, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Idan Alrod, Eran Sharon, Alon Eyal, Liang Pang, Evgeny Mekhanik
  • Updating resistive memory
    Patent number: 9947399
    Abstract: Data is initially programmed in a portion of ReRAM in parallel. Subsequently, one or more ReRAM cells in the portion are determined to contain first data that is to be modified while remaining ReRAM cells in the portion contain second data that is not to be modified. First conditions are applied to the one or more ReRAM cells thereby modifying the first data, while second conditions are applied to the remaining ReRAM cells, the second conditions maintaining the second data in the remaining ReRAM cells without significant change.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: April 17, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ariel Navon, Idan Alrod, Eran Sharon, Idan Goldenberg, Didi Gur
  • Rewritable multibit non-volatile memory with soft decode optimization
    Patent number: 9946468
    Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 17, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Kevin Michael Conley, Raul-Adrian Cernea, Eran Sharon, Idan Alrod
  • ECC decoding using raid-type parity
    Patent number: 9940194
    Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The data structure further includes stripe parity corresponding to portions of the codewords encoded according to a stripe correction scheme. The controller is configured, in response to the number of the undecodable codewords exceeding an erasure correction capacity of the stripe correction scheme, to provide information from a stripe decoding operation to an input of a ECC decoding operation corresponding to an undecodable codeword.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: April 10, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Stella Achtenberg, Eran Sharon, Idan Alrod
  • ECC AND RAID-TYPE DECODING
    Publication number: 20180091172
    Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to read a codeword from a physical location of the memory. The controller is configured to write an inverse bit string to the physical location of the memory, the inverse bit string based on the codeword. The controller is configured to read a representation of the inverse bit string from the physical location of the memory. The controller is further configured to designate one or more bits of the codeword as one or more erased bits based on the codeword and the representation of the inverse bit string.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 29, 2018
    Inventors: ISHAI ILANI, IDAN ALROD, ERAN SHARON, MAI GHALY
  • COLUMN-LAYERED MESSAGE-PASSING LDPC DECODER
    Publication number: 20180062666
    Abstract: In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.
    Type: Application
    Filed: August 23, 2016
    Publication date: March 1, 2018
    Inventors: XINMIAO ZHANG, ALEXANDER BAZARSKY, RAN ZAMIR, ERAN SHARON, IDAN ALROD, OMER FAINZILBER, SANEL ALTERMAN
  • BAD COLUMN HANDLING IN FLASH MEMORY
    Publication number: 20180024880
    Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.
    Type: Application
    Filed: September 20, 2017
    Publication date: January 25, 2018
    Inventors: Damian Yurzola, Eran Sharon, Idan Alrod, Michael Altshuler, Madhuri Kotagiri, Rajeev Nagabhirava
  • Data storage device with a memory die that includes an interleaver
    Patent number: 9875156
    Abstract: A data storage device includes a set of latches, read/write circuitry, a memory, and an interleaver. The set of latches is configured to receive data. The read/write circuitry is coupled to the set of latches. The memory is coupled to the read/write circuitry. The interleaver is configured to interleave the data and to cause the read/write circuitry to program the interleaved data to the memory. The set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: January 23, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Eran Sharon, Ariel Navon, Alexander Tsang-Nam Chu, Wanfang Tsai, Idan Alrod
  • Burn-in memory testing
    Patent number: 9865360
    Abstract: A method performed by a controller includes initiating a first data write operation and an erase operation on a portion of a non-volatile memory. The first data write operation corresponds to a first write resolution. The method includes initiating a second data write operation to write test data to the portion of the non-volatile memory. The second data write operation corresponds to a second write resolution that is greater than the first write resolution. The method also includes reading a representation of the test data from the portion of the non-volatile memory.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: January 9, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Eran Sharon, Alexander Bazarsky, Ariel Navon, Alon Eyal, Idan Alrod, Ofer Shapira
  • TEMPERATURE VARIATION COMPENSATION
    Publication number: 20170345510
    Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a temperature-based value of a search parameter in response to detecting that an error rate of a codeword read from the memory exceeds a threshold error rate. The controller is further configured to iteratively modify one or more memory access parameters associated with reducing temperature-dependent threshold voltage variation and to re-read the codeword using the modified one or more memory access parameters.
    Type: Application
    Filed: June 9, 2017
    Publication date: November 30, 2017
    Inventors: Stella Achtenberg, Eran Sharon, David Rozman, Alon Eyal, Idan Alrod, Dana Lee
  • Bad column handling in flash memory
    Patent number: 9792174
    Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: October 17, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Damian Pablo Yurzola, Eran Sharon, Idan Alrod, Michael Altshuler, Madhuri Kotagiri, Rajeev Nagabhirava
  • Error detection and handling for a data storage device
    Patent number: 9785501
    Abstract: A data storage device includes a non-volatile memory and a controller. A method includes writing a first logical page to a physical page of the non-volatile memory. In response to a multistate error indication satisfying a threshold, the method further includes rewriting the first logical page at the non-volatile memory. The multistate error indication is determined based on the first logical page.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: October 10, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Idan Alrod, Eran Sharon
  • STORAGE DEVICE OPERATIONS BASED ON BIT ERROR RATE (BER) ESTIMATE
    Publication number: 20170269991
    Abstract: A data storage device may include a memory and a controller that includes an error correction coding (ECC) decoder configured to operate in a plurality of decoding modes. The controller also includes a bit error rate estimator configured to determine, based on data received from the memory, bit error rate estimates for ECC codewords from the memory. The controller also includes a data path management unit configured to reorder the codewords based on the bit error rate estimates and to provide the reordered codewords to the ECC decoder.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Alexander Bazarsky, ERAN SHARON, YURI RYABININ, YAN DUMCHIN, IDAN ALROD, ARIEL NAVON
  • ERROR CORRECTION CODE PROCESSING AND DATA SHAPING
    Publication number: 20170269839
    Abstract: A device includes a memory and a controller including a data shaping engine. The data shaping engine is configured to apply a mapping to input data that includes one or more m-tuples of bits to generate transformed data. The transformed data includes one or more n-tuples of bits, and n is greater than m. A relationship of a gray coding of m-tuples to a gray coding of n-tuples is indicated by the mapping. The input data includes a first number of bit values that represent a particular logical state, and the transformed data includes a second number of bit values that represent the particular logical state, the second number of bit values being less than the first number of bit values.
    Type: Application
    Filed: March 17, 2016
    Publication date: September 21, 2017
    Inventors: Idan Alrod, Eran Sharon, Ariel Navon