Abstract: Embodiments of the present disclosure relate to a polyurethane foam, a refrigerator including the same, and a method of manufacturing polyurethane foam. According with the present inventions, a refrigerator, comprising a polyurethane foam formed of a composition for preparing polyurethane, includes a cabinet; a door configured to open and close the cabinet; and a thermal insulation disposed in at least one of the cabinet and the door, wherein the thermal insulation includes a polyurethane foam-forming polyol system comprising a fiber having hydroxyl groups; and isocyanate.

Abstract: A machine behavior classification system may include an electronic data collection system and an electronic data analysis system. The electronic data collection system may have an image capture apparatus that is configured to monitor a machine and the image capture apparatus may produce an image data file of the machine. Moreover, the electronic data analysis system may include a data analytics module that is configured to receive the image data file and the data analytics module may perform a data analysis of the image data file.

Abstract: A pogo pin may include a housing, a resilient connecting member and a switching unit. The housing may be arranged between a printed circuit board (PCB) and a probing head. The resilient connecting member may be arranged in the housing to electrically connect the PCB with the probing head. The switching unit may be provided in the housing to selectively cut off an electrical connection between the PCB and the probing head. Thus, because the PCB may not require additional switching substrates, the PCB may have a small size so that the probe card may also have a small size. A semiconductor device may be manufactured using the probe card.

Abstract: An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.

Abstract: Disclosed is a method for operating an electronic device. A method for operating an electronic device may include: determining an angle between a first body and a second body in an electronic device including the first body having a first display and the second body having a second display, the second body being rotatably connected to the first body; determining a movement state of the electronic device; and displaying a first screen on the first display and displaying a second screen on the second display based on the determined movement state of the electronic device and the determined angle.

Abstract: Provided are a method of preparing an antibody with a regulated, sugar chain content, the method including the step of culturing antibody-expressing cells in a medium including glycerol as an additive for regulating the antibody sugar chain content, a method of preparing a high-quality population of antibodies by regulating the sugar content of the antibody to a desired content, and a population of antibodies prepared by the method. Further, provided is a method of regulating the antibody sugar chain content, the method including the step of culturing antibody-expressing cells in a medium including glycerol as an additive for regulating the antibody sugar chain content. Furthermore, provided is a medium composition, for regulating the antibody sugar chain content, the medium composition including glycerol as an additive for regulating the antibody sugar chain content.

Abstract: In a method of forming an oxide layer of a semiconductor process, a preliminary precursor flow is provided on a substrate in a deposition chamber to form a preliminary precursor layer, a precursor flow and a first oxidizing agent flow are provided on the preliminary precursor layer alternately and repeatedly to form precursor layers and first oxidizing agent layers alternately stacked on the preliminary precursor layer, and a second oxidizing agent flow is provided on the precursor layer or the first oxidizing agent layer alternately stacked to form a second oxidizing agent layer.

Abstract: A method for manufacturing a semiconductor structure includes preparing a semiconductor substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the semiconductor substrate in the memory cell region; forming a bit line structure over the semiconductor substrate in the memory cell region; forming a dielectric layer in the peripheral circuit region and the memory cell region; forming a first opening in the dielectric layer in the memory cell region; filling a silicon filler in the first opening; forming a second opening in the dielectric layer in the peripheral circuit region; forming a sidewall spacer over a sidewall of the second opening; recessing the silicon filler to form a silicon plug, wherein the silicon plug fills a lower portion of the first opening; and forming a first metal silicide over a top surface of the silicon plug, and concurrently forming a second metal silicide in a lower portion of the second opening.

Abstract: A display device is disclosed. In one aspect, the display device includes a substrate including a display area and a non-display area and an input wiring portion and an output wiring portion formed in the non-display area. The display device also includes a driver integrated circuit (IC) formed over the substrate and electrically connected to the input and output wiring portions. Each of the input and output wiring portions includes a metal layer and a metal carbide layer that covers the metal layer.

Abstract: A semiconductor integrated circuit includes a scan enable (SE) inverter and a clock (CK) inverter on a substrate, a first multiplex part, and a second multiplex part. The SE inverter and the CK inverter are aligned in a first direction. The first multiplex part includes a first wiring and a first transistor, the first wiring is connected to a power supply voltage part of the SE inverter, and the first wiring and the first transistor share a source region contacting the first wiring. The second multiplex part includes a second wiring and a second transistor, the second wiring is connected to a power supply voltage part of the CK inverter, and the second wiring and the second transistor share a source region contacting the second wiring. The SE inverter and the CK inverter are aligned in a first direction to each other.

Abstract: An electronic device including a plurality of displays and a method for operating the electronic device are provided. The method includes sensing pressure of an input to at least one of the plurality of displays, executing a first function in correspondence with the input if the sensed pressure is equal to or greater than a threshold, and executing a second function different from the first function in correspondence with the input if the sensed pressure is less than the threshold.

Abstract: A method for manufacturing a semiconductor structure includes preparing a semiconductor substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the semiconductor substrate in the memory cell region; forming a bit line structure over the semiconductor substrate in the memory cell region; forming a dielectric layer in the peripheral circuit region and the memory cell region; forming a first opening in the dielectric layer in the memory cell region; filling a silicon filler in the first opening; forming a second opening in the dielectric layer in the peripheral circuit region; forming a sidewall spacer over a sidewall of the second opening; recessing the silicon filler to form a silicon plug, wherein the silicon plug fills a lower portion of the first opening; and forming a first metal silicide over a top surface of the silicon plug, and concurrently forming a second metal silicide in a lower portion of the second opening.

Abstract: An exemplary embodiment of the present invention provides a battery module including a plurality of rechargeable batteries, a holder defining a plurality of storage spaces for holding the rechargeable batteries in a stacked configuration, a housing for enclosing the holder, and including a first cover and a second cover that face each other and press the holder, and a protective circuit module in the housing and configured to control charging and discharging operations of the rechargeable batteries.

Abstract: A touch pad with a simple structure to enable an electronic device to be manufactured more slimly and with low manufacturing costs. The touch pad includes a cover having a plurality of function icons a cover frame to support the cover, the cover frame including a plurality of light guide hollows, and a board, which is engaged with the cover frame and includes touch sensors and luminous elements to illuminate the function icons mounted thereon, the touch sensors and luminous elements being respectively mounted at positions on the board corresponding to the plurality of function icons.

Abstract: A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.

Abstract: A battery module including a plurality of unit cells, a plurality of bus bars electrically connecting the plurality of unit cells, a positive electrode terminal and a negative electrode terminal that are electrically connected and in contact with two ends of the plurality of unit cells, a battery housing accommodating the plurality of unit cells and the bus bars, and detection terminals that are respectively electrically connected to the plurality of bus bars, wherein the detection terminals are exposed outside the battery housing. Accordingly, voltage balancing between the unit cells may be controlled without disassembling the battery module.

Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.

Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.

Abstract: A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.

Abstract: The present invention relates to a carrier for supporting a catalyst for a spacecraft thruster and to a method for preparing the same, and more particularly, to a catalyst carrier for a spacecraft thruster and method for preparing the same, in which the diameter and distribution of pores of the carrier are controlled using a pore inducing material to lengthen the life of the catalyst.