Patents by Inventor IN-SUNG YEO
IN-SUNG YEO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10709528Abstract: Disclosed are a method for designing dental prosthesis, an apparatus for the same, and a recording medium for recording the same. According to the method, sore spots on which a patient may feel pain due to wearing a dental prosthesis are predicted based on a sore spot distribution model which has been modeled with a plurality of data, and the dental prosthesis is digitally designed based on the predicted results. Accordingly, it is possible to improve the prediction accuracy of sore spots and rapidly design the prosthesis which is more appropriate for the patient.Type: GrantFiled: February 23, 2016Date of Patent: July 14, 2020Assignees: OSSTEMIMPLANT CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, UNIVERSITY OF ULSAN FOUNDATION FOR INDUSTRY COOPERATIONInventors: Namkug Kim, Mooyong Park, Seongyun Lee, Byunghee Han, Il-Hyung Yang, In-Sung Yeo
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Patent number: 10521969Abstract: The present invention relates to method for simulating mandibular movements, device for the same and recording medium for recording the same. With the method for simulating mandible movements according to the present invention, it is possible to perform the simulation directly on the medical image of the patient and thus simulate the mandibular movements more closely to the actual situation. Therefore, the inaccurate mechanical approximation of the mandibular movement with the articulator according to the conventional art is overcome. In addition, according to the present invention, it is possible to simulate mandibular movements customized to the various states of the patient and specific clinical cases.Type: GrantFiled: February 23, 2016Date of Patent: December 31, 2019Assignees: OSSTEMIMPLANT CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, UNIVERSITY OF ULSAN FOUNDATION FOR INDUSTRY COOPERATIONInventors: Namkug Kim, Mooyong Park, Seongyun Lee, Byunghee Han, Il-Hyung Yang, In-Sung Yeo
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Publication number: 20180336736Abstract: The present invention relates to method for simulating mandibular movements, device for the same and recording medium for recording the same. With the method for simulating mandible movements according to the present invention, it is possible to perform the simulation directly on the medical image of the patient and thus simulate the mandibular movements more closely to the actual situation. Therefore, the inaccurate mechanical approximation of the mandibular movement with the articulator according to the conventional art is overcome. In addition, according to the present invention, it is possible to simulate mandibular movements customized to the various states of the patient and specific clinical cases.Type: ApplicationFiled: February 23, 2016Publication date: November 22, 2018Applicants: OSSTEMIMPLANT CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, UNIVERSITY OF ULSAN FOUNDATION FOR INDUSTRY COOPERATIONInventors: Namkug KIM, Mooyong PARK, Seongyun LEE, Byunghee HAN, IL-HYUNG YANG, IN-SUNG YEO
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Publication number: 20180333235Abstract: The present invention relates to a method for designing dental prosthesis, an apparatus for the same, and a recording medium for recording the same. According to the method, sore spots on which a patient may feel pain due to wearing a dental prosthesis are predicted based on a sore spot distribution model which has been modeled with a plurality of data, and the dental prosthesis is digitally designed based on the predicted results. Accordingly, it is possible to improve the prediction accuracy of sore spots and rapidly design the prosthesis which is more appropriate for the patient.Type: ApplicationFiled: February 23, 2016Publication date: November 22, 2018Applicants: OSSTEMIMPLANT CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, UNIVERSITY OF ULSAN FOUNDATION FOR INDUSTRY COOPERATIONInventors: Namkug KIM, Mooyong PARK, Seongyun LEE, Byunghee HAN, IL-HYUNG YANG, IN-SUNG YEO
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Patent number: 9673195Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.Type: GrantFiled: April 29, 2014Date of Patent: June 6, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Man-Hyoung Ryoo, Gi-Sung Yeo, Si-Hyeung Lee, Gyu-Chul Kim, Sung-Gon Jung, Chang-Min Park, Hoo-Sung Cho
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Publication number: 20140231925Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.Type: ApplicationFiled: April 29, 2014Publication date: August 21, 2014Inventors: Man-Hyoung RYOO, Gi-Sung YEO, Si-Hyeung LEE, Gyu-Chul KIM, Sung-Gon JUNG, Chang-Min PARK, Hoo-Sung CHO
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Patent number: 8278221Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.Type: GrantFiled: July 13, 2011Date of Patent: October 2, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-won Koh, Han-ku Cho, Jeong-lim Nam, Gi-sung Yeo, Joon-soo Park, Ji-young Lee
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Patent number: 8193047Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.Type: GrantFiled: January 4, 2010Date of Patent: June 5, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Man-Hyoung Ryoo, Gi-Sung Yeo, Si-Hyeung Lee, Gyu-Chul Kim, Sung-Gon Jung, Chang-Min Park, Hoo-Sung Cho
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Publication number: 20110269294Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.Type: ApplicationFiled: July 13, 2011Publication date: November 3, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cha-won Koh, Han-ku Cho, Jeong-lim Nam, Gi-sung Yeo, Joon-soo Park, Ji-young Lee
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Patent number: 8026044Abstract: A method of forming fine patterns on a semiconductor substrate includes forming a first pattern, including first line patterns having a feature size F and an arbitrary pitch P, and forming a second pattern, including second line patterns disposed between adjacent first line patterns, to form a fine pattern having a half pitch P/2, the first and second line patterns being repeated in the first direction. A gap is formed in at least one first line pattern in a second direction, perpendicular to the first direction, to connect second line patterns positioned on each side of the first line pattern through the gap. At least one jog pattern, extending in the first direction, is formed from at least one first line pattern adjacent to the connected second line patterns. The jog pattern causes a gap in at least one of the connected second line patterns in the second direction.Type: GrantFiled: July 24, 2007Date of Patent: September 27, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-youl Lee, Han-ku Cho, Suk-joo Lee, Gi-sung Yeo, Pan-suk Kwak, Min-jong Hong
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Patent number: 8013374Abstract: A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.Type: GrantFiled: May 13, 2009Date of Patent: September 6, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-Hoon Goo, Han-Ku Cho, Joo-Tae Moon, Sang-Gyun Woo, Gi-Sung Yeo, Kyoung-Yun Baek
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Patent number: 8013375Abstract: A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair.Type: GrantFiled: May 13, 2009Date of Patent: September 6, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Duo-Hoon Goo, Han-Ku Cho, Joo-Tac Moon, Sang-Gyun Woo, Gi-Sung Yeo, Kyoung-Yun Baek
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Patent number: 8003543Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.Type: GrantFiled: April 14, 2010Date of Patent: August 23, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-won Koh, Han-ku Cho, Jeong-lim Nam, Gi-sung Yeo, Joon-soo Park, Ji-young Lee
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Publication number: 20110156159Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Inventors: Man-Hyoung Ryoo, Gi-Sung Yeo, Si-Hyeung Lee, Gyu-Chul Kim, Sung-Gon Jung, Chang-Min Park, Hoo-Sung Cho
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Patent number: 7873935Abstract: A method of manufacturing a mask includes designing a first mask data pattern, designing a second mask data pattern for forming the first mask data pattern, acquiring a first emulation pattern, which is predicted from the second mask data pattern, using layout-based Self-Aligning Double Patterning (SADP) emulation, comparing the first emulation pattern with the first mask data pattern, and modifying the second mask data pattern according to results of the comparison. The method further includes performing Optical Proximity Correction (OPC) on the modified second mask data pattern, acquiring second emulation patterns, which are predicted from the second mask data pattern on which the OPC has been performed, using image-based SADP emulation, and comparing the second emulation patterns and the first mask data pattern and manufacturing a first mask layer, which corresponds to the second mask data pattern on which the OPC has been performed, according to the results of the comparison.Type: GrantFiled: June 14, 2007Date of Patent: January 18, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-gon Jung, Ji-young Lee, Han-ku Cho, Gi-sung Yeo
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Patent number: 7862988Abstract: Provided is a method for forming patterns of a semiconductor device. According to the method, first mask patterns may be formed on a substrate, and second mask patterns may be formed on sidewalls of each first mask pattern. Third mask patterns may fill spaces formed between adjacent second mask patterns, and the second mask patterns may be removed. A portion of the substrate may then be removed using the first and third mask patterns as etch masks.Type: GrantFiled: September 29, 2006Date of Patent: January 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-Won Koh, Yool Kang, Sang-Gyun Woo, Seok-Hwan Oh, Gi-Sung Yeo, Ji-Young Lee
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Patent number: 7842451Abstract: Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern.Type: GrantFiled: July 29, 2009Date of Patent: November 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-Won Koh, Sang-Gyun Woo, Gi-Sung Yeo, Myoung-Ho Jung
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Publication number: 20100290285Abstract: Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.Type: ApplicationFiled: July 29, 2010Publication date: November 18, 2010Inventors: Doo-youl Lee, Han-ku Cho, Suk-joo Lee, Gi-sung Yeo, Cha-won Koh, Pan-suk Kwak
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Patent number: 7795099Abstract: A semiconductor device having a fin type active area includes a plurality of active regions, a first device isolation layer and a recessed second device isolation layer disposed in a direction of gate electrodes of the semiconductor device. A recessed second device isolation layer and a first device isolation layer are disposed in a vertical direction of the gate electrodes. The first device isolation layer and the plurality of active regions are alternately disposed in a first direction of the plurality of active regions.Type: GrantFiled: November 8, 2007Date of Patent: September 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-jae Kang, Ji-young Lee, Han-ku Cho, Gi-sung Yeo
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Patent number: D1021501Type: GrantFiled: September 8, 2022Date of Patent: April 9, 2024Assignee: LG ELECTRONICS INC.Inventors: Hyunggon Ryu, Hyejin Kim, Junhee Yeo, Sung-Gul Hwang