Abstract: Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.

Abstract: Disclosed is an E-beam lithography system for synchronously irradiating surfaces of a plurality of substrates. The E-beam lithography system may include a loading unit loading and unloading substrates, an alignment chamber aligning the substrates, a transfer chamber transferring the substrates from the loading unit or chambers, a lithography chamber radiating one or more electron beams onto the substrates, and a vacuum chamber creating a vacuum in the chambers. A stage may be installed in the lithography chamber such that the substrates may be mounted on the stage and radiated with one or more electron beams.

Abstract: A method of forming fine metal interconnect patterns includes forming an insulating film on a substrate, forming a plurality of mold patterns with first spaces therebetween on the insulating film, such that the mold patterns have a first layout, forming metal hardmask patterns in the first spaces by a damascene process, removing the mold patterns, etching the insulating film through the metal hardmask patterns to form insulating film patterns with second spaces therebetween, the second spaces having the first layout, and forming metal interconnect patterns having the first layout in the second spaces by the damascene process.

Abstract: In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.

Abstract: Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern.

Abstract: Mask sets are provided which may be used to define a first pattern region that has a first pitch pattern and a second pattern region that has a second pitch pattern during the fabrication of a semiconductor device. These mask sets may include a first mask that has a first exposure region in which a first halftone pattern defines the first pattern region and a first screen region in which a first shield layer covers the second pattern region. These mask sets may further include a second mask that has a second exposure region in which a second halftone pattern defines the second pattern region and a second screen region in which a second shield layer covers the first pattern region. The second shield layer also extends from the second screen region to cover a portion of the second halftone pattern.

Abstract: A semiconductor memory device may include a semiconductor substrate having an active region thereof, and the active region may have a length and a width, with the length being greater than the width. A field isolation layer may be on the semiconductor substrate surrounding the active region. First and second wordlines may be on the substrate crossing the active region, with the first and second wordlines defining a drain portion of the active region between the first and second wordlines and first and second source portions of the active region at opposite ends of the active region. First and second memory storage elements may be respectively coupled to the first and second source portions of the active region, with the first and second wordlines being between portions of the respective first and second memory storage elements and the active region in a direction perpendicular to a surface of the substrate.

Abstract: A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.

Abstract: A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair.

Abstract: There are provided a semiconductor device having an overlay measurement mark, and a method of fabricating the same. The semiconductor device includes a scribe line region disposed on a semiconductor substrate. A first main scale layer having a first group of line and space patterns and a second group of line and space patterns is disposed on the scribe line region. Line-shaped second main scale patterns are disposed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are disposed on space regions of the second group of the line and space patterns. In the method, a first main scale layer having a first group of line and space patterns and a second group of line and space patterns is formed on a semiconductor substrate. Line-shaped second main scale patterns are formed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are formed on space regions of the second group of the line and space patterns.

Abstract: Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern.

Abstract: There are provided methods of performing a photolithography process for forming asymmetric semiconductor patterns and methods of forming a semiconductor device using the same. These methods provide a way of forming asymmetric semiconductor patterns on a photoresist layer through two exposure processes. To this end, a semiconductor substrate is prepared. A planarized insulating interlayer and a photoresist layer are sequentially formed on the overall surface of the semiconductor substrate. A first semiconductor pattern of a photolithography mask is transferred to the photoresist layer, thereby forming a photoresist pattern on the photoresist layer. A second semiconductor pattern of a second photolithography mask is continuously transferred to the photoresist layer, thereby forming a second photoresist pattern on the photoresist layer.

Abstract: A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width in a direction of a second axis, and the length may be greater than the width. The plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis, and active regions of adjacent columns may be offset in the direction of the second axis.

Abstract: Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern.

Abstract: A method of manufacturing a mask includes designing a second mask data pattern for forming a first mask data pattern, creating a first emulation pattern, which is determined from the second mask data pattern, using a first emulation, creating a second emulation pattern, which is determined from the first emulation pattern, using a second emulation, comparing a pattern, in which the first and second emulation patterns overlap, with the first mask data pattern, and manufacturing a mask layer, which corresponds to the second mask data pattern, according to results of the comparison.

Abstract: A multiple exposure system and a multiple exposure method using the same enhance the resolution of the image of the mask pattern transferred to a substrate. The system includes NA controllers that provide excellent resolution with respect to the directions of the short axis and long axis of the mask pattern. In one form of the method, a first exposure process is performed using a first NA controller that provides excellent resolution with respect to the direction of the short axis of the mask pattern and subsequently, a second exposure process is performed using a second NA controller that provides excellent resolution with respect to the direction of the long axis of the mask pattern. Alternatively, the first exposure process and the second or high order exposure process can be sequentially performed using the first and second NA controllers simultaneously.

Abstract: In the method of forming a mask structure, a first mask is formed on a substrate where the first mask includes a first mask pattern having a plurality of mask pattern portions having openings therebetween and a second mask pattern having a corner portion of which an inner side wall that is curved. A sacrificial layer is formed on the first mask. A hard mask layer is formed on the sacrificial layer. After the hard mask layer is partially removed until the sacrificial layer adjacent to the corner portion is exposed, a second mask is formed from the hard mask layer remaining in the space after removing the sacrificial layer. A minute pattern having a fine structure may be easily formed on the substrate.