Patents by Inventor Israel Beinglass
Israel Beinglass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8541819Abstract: A semiconductor device including: a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between; where the at least one conductive layer includes a first conductive layer overlaying a second conductive layer overlying a third conductive layer, and where the second conductive layer having a predetermined second layer current carrying capacity greater than the current carrying capacity of the first conductive layer, and the second conductive layer current carrying capacity being greater than the current carrying capacity of the third conductive layer.Type: GrantFiled: December 9, 2010Date of Patent: September 24, 2013Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar
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Patent number: 8405420Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.Type: GrantFiled: August 19, 2010Date of Patent: March 26, 2013Assignee: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, J. L. de Jong, Deepak C. Sekar
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Patent number: 8395191Abstract: A semiconductor device including a first single crystal layer with first transistors and a first alignment mark; at least one metal layer overlying the first single crystal layer, wherein the at least one metal layer includes copper or aluminum; and a second layer including activated dopant regions, the second layer overlying the at least one metal layer, wherein the second layer includes second transistors, wherein the second transistors are processed aligned to the first alignment mark with less than 100 nm alignment error, and the second transistors include mono-crystal, horizontally-oriented transistors.Type: GrantFiled: October 7, 2010Date of Patent: March 12, 2013Assignee: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar, Zeev Wurman
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Patent number: 8378494Abstract: A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.Type: GrantFiled: June 16, 2011Date of Patent: February 19, 2013Assignee: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
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Patent number: 8362482Abstract: A semiconductor device including a first layer including first transistors, wherein first logic circuits are constructed by the first transistors, and wherein the first logic circuits include at least one of Inverter, NAND gate, or NOR gate; and a second layer overlaying said first layer, the second layer including second transistors, wherein second logic circuits are constructed by the second transistors; wherein each logic circuit in the first logic circuits has inputs and at least one first output, the inputs are connected to the second logic circuits; wherein each logic circuit in the second logic circuits has a second output, and wherein the first transistors include first selectors adapted to selectively replace at least one of the at least one first outputs with at least one of the second outputs.Type: GrantFiled: January 28, 2011Date of Patent: January 29, 2013Assignee: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar, Paul Lim
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Publication number: 20120273955Abstract: A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.Type: ApplicationFiled: June 8, 2012Publication date: November 1, 2012Applicant: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar, Zeev Wurman
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Patent number: 8294159Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.Type: GrantFiled: March 28, 2011Date of Patent: October 23, 2012Assignee: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
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Publication number: 20120248595Abstract: A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.Type: ApplicationFiled: June 8, 2012Publication date: October 4, 2012Applicant: MonolithlC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Ze'ev Wurman, Paul Lim
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Patent number: 8273610Abstract: A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.Type: GrantFiled: October 14, 2011Date of Patent: September 25, 2012Assignee: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Ze'ev Wurman, Paul Lim
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Publication number: 20120223738Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.Type: ApplicationFiled: May 14, 2012Publication date: September 6, 2012Applicant: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk De Jong
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Patent number: 8237228Abstract: A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.Type: GrantFiled: September 27, 2011Date of Patent: August 7, 2012Assignee: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar, Zeev Wurman
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Publication number: 20120129301Abstract: A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.Type: ApplicationFiled: October 14, 2011Publication date: May 24, 2012Applicant: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Ze'ev Wurman, Paul Lim
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Publication number: 20120107967Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a first monocrystalline layer including first transistors and interconnecting metal layers to perform at least one first electronic function; providing a second monocrystalline layer on top of the metal layers, wherein the second monocrystalline layer includes second transistors to perform at least one second electronic function and substituting the at least one first electronic function with the at least one second electronic function.Type: ApplicationFiled: December 8, 2011Publication date: May 3, 2012Applicant: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
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Patent number: 8153499Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks and at least one of the second alignment marks.Type: GrantFiled: September 27, 2011Date of Patent: April 10, 2012Assignee: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
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Patent number: 8148728Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.Type: GrantFiled: March 28, 2011Date of Patent: April 3, 2012Assignee: Monolithic 3D, Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
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Publication number: 20120032294Abstract: A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.Type: ApplicationFiled: June 16, 2011Publication date: February 9, 2012Applicant: MonolithlC 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar
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Publication number: 20120028436Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks and at least one of the second alignment marks.Type: ApplicationFiled: September 27, 2011Publication date: February 2, 2012Applicant: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
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Publication number: 20120012895Abstract: A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.Type: ApplicationFiled: September 27, 2011Publication date: January 19, 2012Applicant: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar, Zeev Wurman
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Patent number: 8058137Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks in a first direction and at least one of the second alignment marks in a second direction.Type: GrantFiled: April 11, 2011Date of Patent: November 15, 2011Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
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Publication number: 20110233676Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.Type: ApplicationFiled: March 28, 2011Publication date: September 29, 2011Applicant: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong