Patents by Inventor Israel Beinglass
Israel Beinglass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060223323Abstract: A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.Type: ApplicationFiled: June 15, 2006Publication date: October 5, 2006Inventors: Liang-Yuh Chen, Daniel Carl, Israel Beinglass
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Patent number: 7115516Abstract: A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.Type: GrantFiled: October 9, 2001Date of Patent: October 3, 2006Assignee: Applied Materials, Inc.Inventors: Liang-Yuh Chen, Daniel A. Carl, Israel Beinglass
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Patent number: 6954711Abstract: Test substrates used to test semiconductor fabrication tools are reclaimed by reading from a database the process steps performed on each test substrate and selecting a reclamation process from a plurality of reclamation processes, for reclaiming each test substrate. Information identifying the processes performed on each test substrate and the reclamation process selected for each test substrate, may be stored in a test substrate history database. Each test substrate is sorted and placed into a group of test substrates having a common reclamation process assigned to the test substrates of the group. The bins in which the sorted test substrates are stored are each labeled with identifying information including basic or detailed information on the reclamation process selected for the test substrates stored in the bin. The information may also include a list of the test substrates stored in each bin.Type: GrantFiled: May 19, 2003Date of Patent: October 11, 2005Assignee: Applied Materials, Inc.Inventors: Israel Beinglass, Paul V. Miller
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Publication number: 20040236533Abstract: Test substrates used to test semiconductor fabrication tools are reclaimed by reading from a database the process steps performed on each test substrate and selecting a reclamation process from a plurality of reclamation processes, for reclaiming each test substrate. Information identifying the processes performed on each test substrate and the reclamation process selected for each test substrate, may be stored in a test substrate history database. Each test substrate is sorted and placed into a group of test substrates having a common reclamation process assigned to the test substrates of the group. The bins in which the sorted test substrates are stored are each labeled with identifying information including basic or detailed information on the reclamation process selected for the test substrates stored in the bin. The information may also include a list of the test substrates stored in each bin.Type: ApplicationFiled: May 19, 2003Publication date: November 25, 2004Applicant: Applied Materials, Inc.Inventors: Israel Beinglass, Paul V. Miller
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Publication number: 20040077161Abstract: A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.Type: ApplicationFiled: October 9, 2001Publication date: April 22, 2004Applicant: Applied Materials, Inc.Inventors: Liang-Yuh Chen, Daniel A. Carl, Israel Beinglass
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Publication number: 20030182252Abstract: One embodiment of the present invention is a process tool optimization system that includes: (a) a data mining engine that analyzes end-of-line yield data to identify one or more process tools associated with low yield; and (b) in response to output from the analysis, analyzes process tool data from the one or more process tools to identify one or more process tool parameters associated with the low yield.Type: ApplicationFiled: March 21, 2002Publication date: September 25, 2003Applicant: Applied Materials, Inc.Inventors: Israel Beinglass, Amir Feili, Amos Dor
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Patent number: 6402850Abstract: A barrier to prevent reactant gases from reaching the surfaces of a susceptor support for a substrate upon which polysilicon films are to be deposited provides improved uniformity of the depositing film across the substrate, and prevents substrate-to-substrate variations during sequential depositions. A suitable barrier includes a preheat ring extension that mates with an extension of the susceptor support.Type: GrantFiled: September 2, 1994Date of Patent: June 11, 2002Assignee: Applied Materials, Inc.Inventors: Israel Beinglass, Mahalingam Venkatesan, Christian M. Gronet
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Patent number: 6197694Abstract: A method is described for cleaning a silicon surface of a semiconductor wafer in a vacuum chamber while radiantly heating said silicon surface to maintain it within a first temperature range in the presence of hydrogen gas; then quickly cooling the wafer down to a second temperature range by reducing the radiant heat; and then forming a layer of either polysilicon or oxide over the cleaned surface within this second temperature range without removing the cleaned wafer from the chamber. By cleaning the wafer and then depositing polysilicon or growing oxide over the cleaned silicon surface in the same vacuum chamber, formation of oxides and other contaminants on the cleaned silicon surface between the cleaning step and the deposition or growth step is inhibited, resulting in a higher quality polysilicon or oxide layer formed over the cleaned silicon surface.Type: GrantFiled: July 31, 1996Date of Patent: March 6, 2001Assignee: Applied Materials, Inc.Inventor: Israel Beinglass
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Patent number: 6169030Abstract: The invention generally provides an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free interconnections in high aspect ratio, sub-half micron applications. The invention provides a multi-step PVD process in which the plasma power is varied for each of the steps to obtain favorable fill characteristics as well as good reflectivity, morphology and throughput. The initial plasma powers are relatively low to ensure good, void-free filling of the aperture and, then, the plasma powers are increased to obtain the desired reflectivity and morphology characteristics. The invention provides an aperture filling process comprising physical vapor depositing a metal over the substrate and varying the plasma power during the physical vapor deposition. Preferably, the plasma power is varied from a first discrete low plasma power to a second discrete high plasma power.Type: GrantFiled: January 14, 1998Date of Patent: January 2, 2001Assignee: Applied Materials, Inc.Inventors: Mehul B. Naik, Ted Guo, Liang-Yuh Chen, Roderick Craig Mosely, Israel Beinglass
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Patent number: 6146464Abstract: An apparatus for depositing a material on a wafer includes a susceptor plate mounted in a deposition chamber. The chamber has a gas inlet and a gas exhaust. Means are provided for heating the susceptor plate. The susceptor plate has a plurality of support posts projecting from its top surface. The support posts are arranged to support a wafer thereon with the back surface of the wafer being spaced from the surface of the susceptor plate. The support posts are of a length so that the wafer is spaced from the susceptor plate a distance sufficient to allow deposition gas to flow and/or diffuse between the wafer and the susceptor plate, but still allow heat transfer from the susceptor plate to the wafer mainly by conduction. The susceptor plate is also provided with means, such as retaining pins or a recess, to prevent lateral movement of a wafer seated on the support posts.Type: GrantFiled: June 30, 1997Date of Patent: November 14, 2000Assignee: Applied Materials, Inc.Inventors: Israel Beinglass, Mahalingam Venkatesan, Roger N. Anderson
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Patent number: 6017144Abstract: The present invention is to a chemical vapor deposition process for depositing a substantially planar, highly reflective layer on a substrate, and is particularly useful for filling high aspect ratio holes in the substrate with metal-containing material. The substrate is placed in a process zone, and successive seeding and oriented crystal growth stages are performed on the substrate. In the seeding stage, the substrate is heated to temperatures T.sub.s, within a first lower range of temperatures .DELTA. T.sub.s, and a seeding gas is introduced into the process zone. The seeding gas deposits a substantially continuous, non-granular, and planar seeding layer on the substrate. Thereafter, in an oriented crystal growth stage, the substrate is maintained at deposition temperatures T.sub.d, within a second higher range of temperatures .DELTA. T.sub.D, and deposition gas is introduced into the process zone.Type: GrantFiled: October 24, 1996Date of Patent: January 25, 2000Assignee: Applied Materials, Inc.Inventors: Ted Tie Guo, Mehul Bhagubhai Naik, Liang-Yu Chen, Roderick Craig Mosely, Israel Beinglass
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Patent number: 5940733Abstract: Described is an improved polysilicon/tungsten silicide (WSi.sub.x) composite layer formed over an integrated circuit structure on a semiconductor wafer and characterized by improved step coverage and non tungsten-rich tungsten:silicon ratio of the WSi.sub.x layer, and a method of forming same. A doped layer of polysilicon is formed in a first deposition chamber over an integrated circuit structure previously formed on a semiconductor substrate and a capping layer of undoped polysilicon is then deposited in the first deposition chamber over the doped polysilicon layer. The substrate is then transferred from the first deposition chamber into a second deposition chamber without exposing the surface of the polysilicon layer to an oxidizing media.Type: GrantFiled: July 29, 1997Date of Patent: August 17, 1999Assignee: Applied Materials, Inc.Inventors: Israel Beinglass, Ramanujapuram A. Srinivas
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Patent number: 5932286Abstract: Thin, uniform films of silicon nitride can be deposited onto a single substrate in a low pressure chemical vapor deposition process at a practicable rate from a gas mixture including a silane precursor gas and ammonia by maintaining the pressure at between about 5 and about 100 Torr. Deposition rates of up to about 185 angstroms per minute are readily achieved.Type: GrantFiled: March 16, 1993Date of Patent: August 3, 1999Assignee: Applied Materials, Inc.Inventors: Israel Beinglass, Mahalingam Venkatesan
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Patent number: 5876797Abstract: A method of producing doped and undoped silicon layers on a substrate by chemical vapor deposition at elevated pressures of from about 10 to about 350 Torr whereby deposition occurs at practicable rates. A substrate is loaded in a vacuum chamber, the temperature adjusted to obtain a silicon deposit of predetermined crystallinity, and the silicon precursor gases fed to the chamber to a preselected high pressure. Both undoped and doped silicon can be deposited at high rates up to about 3000 angstroms per minute.Type: GrantFiled: October 8, 1997Date of Patent: March 2, 1999Assignee: Applied Materials, Inc.Inventors: Israel Beinglass, David K. Carlson
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Patent number: 5874129Abstract: A method of producing amorphous silicon layers on a substrate by chemical vapor deposition at elevated pressures of at least about 25 Torr whereby deposition occurs at practicable rates. A substrate is loaded in a vacuum chamber, the temperature adjusted to obtain an amorphous silicon deposit of predetermined microcrystalline density, and the silicon precursor gases fed to the chamber to a preselected high pressure. Doped amorphous silicon films also can be deposited at high deposition rates.The above amorphous silicon films have a low density of nucleation sites; thus when the films are annealed, polycrystalline films having large crystal grains are produced.Type: GrantFiled: December 10, 1996Date of Patent: February 23, 1999Assignee: Applied Materials, Inc.Inventors: Israel Beinglass, Mali Venkatesan
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Patent number: 5834059Abstract: The present disclosure is directed to a process of depositing a layer of a material on a wafer, which comprises depositing a layer of the same material to be deposited on the wafer on the back surface of a susceptor.Type: GrantFiled: March 27, 1996Date of Patent: November 10, 1998Assignee: Applied Materials, Inc.Inventors: Roger N. Anderson, H. Peter W. Hey, Israel Beinglass, Mahalingam Venkatesan
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Patent number: 5725673Abstract: The present disclosure is directed to an apparatus for depositing a layer of a material on a wafer. The apparatus includes a deposition chamber having an upper dome, a lower dome and a side wall between the upper and lower domes. A susceptor plate is in and extends across the deposition chamber to divide the deposition chamber into an upper portion above the susceptor plate and a lower portion below the susceptor plate. An exhaust passage formed through the side wall and is coupled to an upper passage which extends to the upper portion of the deposition chamber and is coupled to a lower passage which extends to the lower portion of the deposition chamber.Type: GrantFiled: September 25, 1996Date of Patent: March 10, 1998Assignee: Applied Materials Inc.Inventors: Roger N. Anderson, H. Peter W. Hey, Israel Beinglass, Mahalingam Venkatesan
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Patent number: 5700520Abstract: A method of producing doped and undoped silicon layers on a substrate by chemical vapor deposition at elevated pressures of from about 10 to about 350 Torr whereby deposition occurs at practicable rates. A substrate is loaded in a vacuum chamber, the temperature adjusted to obtain a silicon deposit of predetermined crystallinity, and the silicon precursor gases fed to the chamber to a preselected high pressure. Both undoped and doped silicon can be deposited at high rates up to about 3000 angstroms per minute.Type: GrantFiled: June 19, 1996Date of Patent: December 23, 1997Assignee: Applied Materials, Inc.Inventors: Israel Beinglass, David K. Carlson
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Patent number: 5695819Abstract: A thermal decomposition CVD method is provided for forming a polysilicon layer over a stepped surface on a semiconductor wafer. The method includes introducing a continuous flow of silicon precursor gases into a vacuum chamber, and adjusting the flow rates and concentrations of the precursor gases, adjusting the temperature and adjusting the pressure within the vacuum chamber so as to control the growth rate of the polysilicon layer on the substrate to between about 500 angstroms/minute and about 2000 angstroms/minute. In a preferred embodiment of the invention, the growth rate of the polysilicon layer is controlled by adjusting the precursor gas flow rates, the temperature and the pressure to between about 1000 angstroms/minute and about 1500 angstroms/minute with the result that the average step coverage of the polysilicon layer is greater than about 95 percent.Type: GrantFiled: May 2, 1996Date of Patent: December 9, 1997Assignee: Applied Materials, Inc.Inventors: Israel Beinglass, Mahalingam Venkatesan
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Patent number: 5645646Abstract: An apparatus for depositing a material on a wafer includes a susceptor plate mounted in a deposition chamber. The chamber has a gas inlet and a gas exhaust. Means are provided for heating the susceptor plate. The susceptor plate has a plurality of support posts projecting from its top surface. The support posts are arranged to support a wafer thereon with the back surface of the wafer being spaced from the surface of the susceptor plate. The support posts are of a length so that the wafer is spaced from the susceptor plate a distance sufficient to allow deposition gas to flow and/or diffuse between the wafer and the susceptor plate, but still allow heat transfer from the susceptor plate to the wafer mainly by conduction. The susceptor plate is also provided with means, such as retaining pins or a recess, to prevent lateral movement of a wafer seated on the support posts.Type: GrantFiled: November 14, 1996Date of Patent: July 8, 1997Assignee: Applied Materials, Inc.Inventors: Israel Beinglass, Mahalingam Venkatesan, Roger N. Anderson