Patents by Inventor Israel Beinglass

Israel Beinglass has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5614257
    Abstract: A method of producing amorphous silicon layers on a substrate by chemical vapor deposition at elevated pressures of at least about 25 Torr whereby deposition occurs at practicable rates. A substrate is loaded in a vacuum chamber, the temperature adjusted to obtain an amorphous silicon deposit of predetermined microcrystalline density, and the silicon precursor gases fed to the chamber to a preselected high pressure. Doped amorphous silicon films also can be deposited at high deposition rates. The above amorphous silicon films have a low density of nucleation sites; thus when the films are annealed, polycrystalline films having large crystal grains are produced.
    Type: Grant
    Filed: May 18, 1995
    Date of Patent: March 25, 1997
    Assignee: Applied Materials, Inc
    Inventors: Israel Beinglass, Mali Venkatesan
  • Patent number: 5607724
    Abstract: A method of producing doped and undoped polycrystalline silicon layers on a substrate by chemical vapor deposition at elevated pressures of from about 10 to about 350 Torr whereby deposition occurs at practicable rates. A substrate is loaded in a vacuum chamber, the temperature adjusted to obtain a silicon deposit of predetermined crystallinity, and the silicon precursor gases fed to the chamber to a preselected high pressure. Both undoped and doped silicon can be deposited at high rates up to about 3000 angstroms per minute.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: March 4, 1997
    Assignee: Applied Materials, Inc.
    Inventors: Israel Beinglass, David K. Carlson
  • Patent number: 5599397
    Abstract: The present disclosure is directed to an apparatus for depositing a layer of a material on a wafer. The apparatus includes a deposition chamber having an upper dome, a lower dome and a side wall between the upper and lower domes. A susceptor plate is in and extends across the deposition chamber to divide the deposition chamber into an upper portion above the susceptor plate and a lower portion below the susceptor plate. A gas inlet manifold is in the side wall. The manifold has three inlet ports. One of the ports is connected by passages which open into the lower portion of the deposition chamber. The other two ports are connected by passages which open into the upper portion of the deposition chamber. A gas supply system is connected to the inlet ports so as to provide the same gases into the lower portion of the deposition chamber as well as into the upper portion of the deposition chamber.
    Type: Grant
    Filed: March 27, 1996
    Date of Patent: February 4, 1997
    Assignee: Applied Materials Inc.
    Inventors: Roger N. Anderson, H. Peter W. Hey, Israel Beinglass, Mahalingam Venkatesan
  • Patent number: 5576059
    Abstract: A barrier to prevent reactant gases from reaching the surfaces of a susceptor support for a substrate upon which polysilicon films are to be deposited provides improved uniformity of the depositing film across the substrate, and prevents substrate-to-substrate variations during sequential depositions. A suitable barrier includes a preheat ring extension that mates with an extension of the susceptor support.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 19, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Israel Beinglass, Mahalingam Venkatesan, Christian M. Gronet
  • Patent number: 5551982
    Abstract: The present disclosure is directed to an apparatus for depositing a layer of a material on a wafer. The apparatus includes a deposition chamber having an upper dome, a lower dome and a side wall between the upper and lower domes. A susceptor plate is in and extends across the deposition chamber to divide the deposition chamber into an upper portion above the susceptor plate and a lower portion below the susceptor plate. A gas inlet manifold is in the side wall. The manifold has three inlet ports. One of the ports is connected by passages which open into the lower portion of the deposition chamber. The other two ports are connected by passages which open into the upper portion of the deposition chamber. A gas supply system is connected to the inlet ports so as to provide the same gases into the lower portion of the deposition chamber as well as into the upper portion of the deposition chamber.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: September 3, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Roger N. Anderson, H. Peter W. Hey, Israel Beinglass, Mahalingam Venkatesan
  • Patent number: 5352636
    Abstract: A method is described for cleaning a silicon surface of a semiconductor wafer in a vacuum chamber while radiantly heating said silicon surface to maintain it within a first temperature range in the presence of hydrogen gas; then quickly cooling the wafer down to a second temperature range by reducing the radiant heat; and then forming a layer of either polysilicon or oxide over the cleaned surface within this second temperature range without removing the cleaned wafer from the chamber. By cleaning the wafer and then depositing polysilicon or growing oxide over the cleaned silicon surface in the same vacuum chamber, formation of oxides and other contaminants on the cleaned silicon surface between the cleaning step and the deposition or growth step is inhibited, resulting in a higher quality polysilicon or oxide layer formed over the cleaned silicon surface.
    Type: Grant
    Filed: January 16, 1992
    Date of Patent: October 4, 1994
    Assignee: Applied Materials, Inc.
    Inventor: Israel Beinglass
  • Patent number: 5141892
    Abstract: A polysilicon deposition process is disclosed for forming a doped polysilicon layer over a stepped surface on a semiconductor wafer having the deposition characteristics and resulting profile of an undoped polysilicon layer which comprises: depositing doped polysilicon on the stepped surface, depositing undoped polysilicon over the doped polysilicon, repeating the doped and undoped depositions cyclically until the desired amount of polysilicon has been deposited, and then annealing the deposited polysilicon to uniformly distribute the dopant throughout the entire deposited polysilicon layer.
    Type: Grant
    Filed: October 31, 1991
    Date of Patent: August 25, 1992
    Assignee: Applied Materials, Inc.
    Inventor: Israel Beinglass
  • Patent number: 4975385
    Abstract: An improved method is disclosed for forming one or more N- LDD regions in an integrated circuit structure wherein there is no offset between the gate electrode and the source and drain regions in the resulting structure which comprises the steps of: forming a polysilicon gate electrode over a semiconductor wafer substrate, N- doping the substrate to form one or more N- LDD regions, selectively depositing polysilicon on the polysilicon sidewalls of the gate electrode, and then N+ doping the substrate to form N+ source and drain regions in the substrate using the selectively deposited polysilicon as a mask over the N- LDD regions previously formed in the substrate.
    Type: Grant
    Filed: April 6, 1990
    Date of Patent: December 4, 1990
    Assignee: Applied Materials, Inc.
    Inventors: Israel Beinglass, John Borland
  • Patent number: 4446613
    Abstract: A process for forming a resistor structure which comprises a polysilicon strip having a resistor region with tungsten leads formed on opposite ends of the strip. A protective oxide is grown on the sides of the silicon strip preventing undercutting of the oxide layer disposed beneath this strip. This prevents formation of the tungsten under the strip or along the sides of the strip which would otherwise place stress on the strip in addition causing other problems.
    Type: Grant
    Filed: October 19, 1981
    Date of Patent: May 8, 1984
    Assignee: Intel Corporation
    Inventors: Israel Beinglass, Nan-Hsiung Tsai
  • Patent number: 4441247
    Abstract: A process is described for forming MOS circuits which include underlying polysilicon members such as gate members covered with metal. In one embodiment, a self-aligning tungsten process is used to cover the polysilicon members. Low temperature "rear end" steps are used to prevent deterioration of the underlying metal. For example, a plasma nitride protective layer is used to cover the metal. The polysilicon/metal members provide reduced resistance and increase the speed of the resultant MOS circuits.
    Type: Grant
    Filed: June 29, 1981
    Date of Patent: April 10, 1984
    Assignee: Intel Corporation
    Inventors: Paolo Gargini, Israel Beinglass, Norman Ahlquist
  • Patent number: 4094268
    Abstract: A method and horizontal furnace for vapor phase growth of HgI.sub.2 crystals which utilizes controlled axial and radial airflow to maintain the desired temperature gradients. The ampoule containing the source material is rotated while axial and radial air tubes are moved in opposite directions during crystal growth to maintain a desired distance and associated temperature gradient with respect to the growing crystal, whereby the crystal interface can advance in all directions, i.e., radial and axial according to the crystallographic structure of the crystal. Crystals grown by this method are particularly applicable for use as room-temperature nuclear radiation detectors.
    Type: Grant
    Filed: March 30, 1977
    Date of Patent: June 13, 1978
    Assignee: United States Department of Energy
    Inventors: Michael M. Schieber, Israel Beinglass, Giora Dishon
  • Patent number: 4030964
    Abstract: A method and horizontal furnace for vapor phase growth of HgI.sub.2 crystals which utilizes controlled axial and radial airflow to maintain the desired temperature gradients. The ampoule containing the source material is rotated while axial and radial air tubes are moved in opposite directions during crystal growth to maintain a desired distance and associated temperature gradient with respect to the growing crystal, whereby the crystal interface can advance in all directions, i.e., radial and axial according to the crystallographic structure of the crystal. Crystals grown by this method are particularly applicable for use as room-temperature nuclear radiation detectors.
    Type: Grant
    Filed: April 29, 1976
    Date of Patent: June 21, 1977
    Assignee: The United States of America as represented by the United States Energy Research and Development Administration
    Inventors: Michael M. Schieber, Israel Beinglass, Giora Dishon