Abstract: A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a substrate material and a buried insulating material interposed between the active semiconductor layer and the substrate material, and a bulk semiconductor region that includes the substrate material. An insulating structure is positioned in the hybrid substrate, wherein the insulating structure separates the bulk region from the SOI region, and a gate electrode is positioned above the substrate material in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

Abstract: A semiconductor device includes an SOI substrate having a base substrate material, an active semiconductor layer positioned above the base substrate material and a buried insulating material layer positioned between the base substrate material and the active semiconductor layer. A gate structure is positioned above the active semiconductor layer and a back gate region is positioned in the base substrate material below the gate structure and below the buried insulating material layer. An isolation region electrically insulates the back gate region from the surrounding base substrate material, wherein the isolation region includes a plurality of implanted well regions that laterally contact and laterally enclose the back gate region and an implanted isolation layer that is formed below the back gate region.

Abstract: It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.

Abstract: A method of manufacturing a flash memory cell is provided including forming a plurality of semiconductor fins on a semiconductor substrate, forming floating gates for a sub-set of the plurality of semiconductor fins and forming a first insulating layer between the plurality of semiconductor fins. The first insulating layer is recessed to a height less than the height of the plurality of semiconductor fins and sacrificial gates are formed over the sub-set of the plurality of semiconductor fins. A second insulating layer is formed between the sacrificial gates and, after that, the sacrificial gates are removed. Recesses are formed in the first insulating layer and sense gates and control gates are formed in the recesses for the sub-set of the plurality of semiconductor fins. The first and second insulating layers may be oxide layers.

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an SOI region and a bulk region, the SOI region comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between the active semiconductor layer and the substrate material, and the bulk region being provided by the substrate material, an insulating structure formed in the hybrid substrate, the insulating structure separating the bulk region and the SOI region, and a gate electrode formed in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

Abstract: The present disclosure provides in one aspect a semiconductor device including an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which, in turn, is formed on a base substrate material, a gate structure formed on the active semiconductor layer, and a back gate region provided in the base substrate material below the gate structure opposing the gate structure. Herein, the back gate region may be electrically insulated from the surrounding base substrate material via an isolation region surrounding the back gate region.

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an SOI region and a bulk region, the SOI region comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between the active semiconductor layer and the substrate material, and the bulk region being provided by the substrate material, an insulating structure formed in the hybrid substrate, the insulating structure separating the bulk region and the SOI region, and a gate electrode formed in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

Abstract: It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.

Abstract: A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.

Abstract: A semiconductor device is provided including a fully depleted silicon-on-insulator (FDSOI) substrate and a charge pump device, wherein the FDSOI substrate comprises a semiconductor bulk substrate, and the charge pump device comprises a transistor device formed in and on the FDSOI substrate, and a trench capacitor formed in the semiconductor bulk substrate and electrically connected to the transistor device.

Abstract: A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate, forming a first plurality of semiconductor fins in a logic area of the semiconductor substrate, forming a second plurality of semiconductor fins in a memory area of the semiconductor substrate, forming an insulating layer between the fins of the first plurality of semiconductor fins and between the fins of the second plurality of semiconductor fins, forming an electrode layer over the first and second pluralities of semiconductor fins and the insulating layer, forming gates over semiconductor fins of the first plurality of semiconductor fins in the logic area from the gate electrode layer, and forming sense gates and control gates between semiconductor fins of the second plurality of semiconductor fins in the logic area from the gate electrode layer.

Abstract: The present disclosure provides in one aspect a semiconductor device including an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which, in turn, is formed on a base substrate material, a gate structure formed on the active semiconductor layer, and a back gate region provided in the base substrate material below the gate structure opposing the gate structure. Herein, the back gate region may be electrically insulated from the surrounding base substrate material via an isolation region surrounding the back gate region.

Abstract: A semiconductor device is provided including a substrate, a buried oxide layer formed over the substrate, a semiconductor layer formed over the buried oxide layer, and a transistor device including a gate electrode, a gate insulation layer and a channel region, wherein the gate insulation layer comprises a part of the buried oxide layer.

Abstract: Integrated circuits employing replacement metal gate technologies with separate workfunction material layers and raised source/drain structures and methods for fabricating the same are disclosed herein. In one exemplary embodiment, a method of fabricating an integrated circuit includes forming a first workfunction material layer over an ILD layer, along the sidewall spacer structures, and over the high-k material layer. The method further includes forming a masking layer over the first workfunction material layer, performing a tilted ion implant wherein ions are implanted at the masking layer over the ILD layer and along the sidewall spacer structures, selectively etching the masking layer and the first workfunction material from over the ILD layer and from along the sidewall spacer structures, and forming a second workfunction material layer over the ILD layer, along the sidewall spacer structures, and over the first workfunction material layer.

Abstract: Disclosed is an integrated circuit product comprised of a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only the second PMOS active region has a silicon germanium layer formed thereon, a first PMOS device formed in and above the first PMOS active region, the first PMOS device having a first gate structure, and a second PMOS device formed in and above the second PMOS active region, the second PMOS device having a second gate structure disposed on the silicon germanium layer.

Abstract: The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.

Abstract: A method of forming a semiconductor device is provided including the steps of forming first and second PMOS transistor devices, wherein the first PMOS transistor devices are low, standard or high voltage threshold transistor devices and the second PMOS transistor devices are super high voltage threshold transistor devices, and wherein forming the first PMOS transistor devices includes implanting dopants to form source and drain junctions of the first PMOS transistor devices and performing a thermal anneal of the first PMOS transistor devices after implanting the dopants, and forming the second PMOS transistor devices includes implanting dopants to form source and drain junctions of the second PMOS transistor devices after performing the thermal anneal of the first PMOS transistor devices.

Abstract: A method of forming a spacer is disclosed that involves forming a layer of spacer material above an etch stop layer, performing a first main etching process on the layer of spacer material to remove some of material, stopping the etching process prior to exposing the etch stop layer and performing a second over-etch process on the layer of spacer material, using the following parameters: an inert gas flow rate of about 50-200 sscm, a reactive gas flow rate of about 3-20 sscm, a passivating gas flow rate of about 3-20 sscm, a processing pressure about 5-15 mT, a power level of about 200-500 W for ion generation and a bias voltage of about 300-500 V. A device includes a gate structure positioned above a semiconducting substrate, a substantially triangular-shaped sidewall spacer positioned proximate the gate structure and an etch stop layer positioned between the spacer and the gate structure.

Abstract: A device includes first and second spaced-apart active regions positioned in a semiconducting substrate, an isolation region positioned between and separating the first and second spaced-apart active regions, and a layer of gate insulation material positioned on the first active region. A first conductive line feature extends continuously from the first active region and across the isolation region to the second active region, wherein the first conductive line feature includes a first portion that is positioned directly above the layer of gate insulation material positioned on the first active region and a second portion that conductively contacts the second active region.

Abstract: A device includes first and second spaced-apart active regions positioned in a semiconducting substrate, an isolation region positioned between and separating the first and second spaced-apart active regions, and a layer of gate insulation material positioned on the first active region. A first conductive line feature extends continuously from the first active region and across the isolation region to the second active region, wherein the first conductive line feature includes a first portion that is positioned directly above the layer of gate insulation material positioned on the first active region and a second portion that conductively contacts the second active region.