Abstract: A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

Abstract: A method of forming a doped semiconductor portion includes providing a semiconductor substrate with a surface, and providing protruding portions of a covering layer on the substrate surface, where the portions are arranged in a pattern of lines or segments of lines extending in a first direction. Portions of a resist layer are provided on the substrate surface, where the portions of the resist layer are arranged in a pattern of lines or segments of lines extending in a second direction, and the second direction intersects the first direction. The portions of the resist layer have a thickness d, the thickness d being measured perpendicularly with respect to the substrate surface. A tilted ion implantation step is then performed.

Abstract: One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove.

Abstract: The invention relates to a method of manufacturing a semiconductor device, in which a substrate is provided, a dielectric layer is formed on top of the substrate, an amorphous semiconductor layer id deposited on top of the dielectric layer, the amorphous semiconductor layer is doped, and a high temperature step to the amorphous layer is applied to form a crystallized layer out of the amorphous semiconductor.

Abstract: A process is described which allows a buried, retrograde doping profile or a delta doping to be produced in a relatively simple and inexpensive way. The process uses individual process steps that are already used in the mass production of integrated circuits and accordingly can be configured for a high throughput.

Abstract: The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor substrate (10), having the following steps: application of the gate stacks (GS1, GS2, GS3, GS4) to a gate dielectric (11) above the semiconductor substrate (10); formation of a sidewall oxide (17) on sidewalls of the gate stacks (GS1, GS2, GS3, GS4); application and patterning of a mask (12) on the semiconductor structure; and implantation of a contact doping (13) in a self-aligned manner with respect to the sidewall oxide (17) of the gate stacks (GS1, GS2) in regions not covered by the mask (12).

Abstract: A p-channel field-effect transistor is formed on a semiconductor substrate. The transistor has an n-doped gate electrode, a buried channel, a p-doped source and a p-doped drain. The transistor is fabricated by a procedure in which, after an implantation for defining an n-type well, an oxidation is performed to form a gate-oxide layer and n-doped polysilicon is subsequently deposited. The latter is doped with boron or boron fluoride particles either in situ or by a dedicated implantation step. In a thermal process, the boron acceptors penetrate through the oxide layer into the substrate of the n-type well, where they form a p-doped zone, which serves for counter doping and sets the threshold voltage. This results in a steep profile that permits a shallow buried channel. The control of the number particles penetrating through the oxide layer is achieved by nitriding the oxide layer in an N2O atmosphere.

Abstract: A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; a conductive second filling material filled into the trench as a second capacitor plate; and a buried contact underneath the surface of the substrate. The substrate has, underneath its surface in the region of the buried contact, a doped region introduced by implantation, plasma doping and/or vapor phase deposition. A tunnel layer, in particular an oxide, nitride or oxinitride layer, is preferably formed at the interface of the buried contact. A method for producing a trench capacitor is also provided.

Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

Abstract: A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; a conductive second filling material filled into the trench as a second capacitor plate; and a buried contact underneath the surface of the substrate. The substrate has, underneath its surface in the region of the buried contact, a doped region introduced by implantation, plasma doping and/or vapor phase deposition. A tunnel layer, in particular an oxide, nitride or oxinitride layer, is preferably formed at the interface of the buried contact.

Abstract: A method of fabricating an epitaxial layer includes providing a substrate having a substrate surface with an at least partly uncovered monocrytalline region, and at least one electrically insulating region adjoining the monocrystalline region and being at least partly surrounded by the monocrystalline region. An epitaxial layer is grown on the monocrystalline region. The electrically insulating region is at least partly overgrown laterally with the epitaxial layer, thereby forming an epitaxial closing joint above the electrically insulating region due to the overgrowth. The epitaxial layer is at least partly removed above the electrically insulating region, thereby the epitaxial closing joint is at least partly removed.

Abstract: Corner conduction in a conduction channel of a field effect transistor is controlled by the geometrical configuration of the gate oxide and gate electrode at the sides of the conduction channel. Rounding the corners of the conduction channel or forming depressions at edges of trench structures such as deep or shallow trench isolation structures and/or trench capacitors develop recesses in a surface of a substrate at an interface of active areas and trench structures in which a portion of the gate oxide and gate electrode are formed so that the gate oxide and gate electrode effectively wrap around a portion of the conduction channel of the transistor. Particularly when such transistors are formed in accordance with sub-micron design rules, the geometry of the gate electrode allows the electric field in the conduction channel to be modified without angled implantation to regulate the effects of corner conduction in the conduction channel.

Abstract: Corner conduction in a conduction channel of a field effect transistor is controlled by the geometrical configuration of the gate oxide and gate electrode at the sides of the conduction channel. Rounding the corners of the conduction channel or forming depressions at edges of trench structures such as deep or shallow trench isolation structures and/or trench capacitors develop recesses in a surface of a substrate at an interface of active areas and trench structures in which a portion of the gate oxide and gate electrode are formed so that the gate oxide and gate electrode effectively wrap around a portion of the conduction channel of the transistor. Particularly when such transistors are formed in accordance with sub-micron design rules, the geometry of the gate electrode allows the electric field in the conduction channel to be modified without angled implantation to regulate the effects of corner conduction in the conduction channel.

Abstract: Corner conduction in a conduction channel of a field effect transistor is controlled by the geometrical configuration of the gate oxide and gate electrode at the sides of the conduction channel. Rounding the corners of the conduction channel or forming depressions at edges of trench structures such as deep or shallow trench isolation structures and/or trench capacitors develop recesses in a surface of a substrate at an interface of active areas and trench structures in which a portion of the gate oxide and gate electrode are formed so that the gate oxide and gate electrode effectively wrap around a portion of the conduction channel of the transistor. Particularly when such transistors are formed in accordance with sub-micron design rules, the geometry of the gate electrode allows the electric field in the conduction channel to be modified without angled implantation to regulate the effects of corner conduction in the conduction channel.