Abstract: A semiconductor device according to an embodiment includes a substrate, a bit line structure and a source line structure respectively extending in a direction perpendicular to a surface of the substrate, a semiconductor layer disposed between the bit line structure and the source line structure on a plane parallel to the surface of the substrate, a first ferroelectric layer disposed on a first surface of the semiconductor layer, and a first gate electrode layer disposed on the first ferroelectric layer.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an electrode stack disposed on the substrate, the electrode stack including an interlayer insulation layer and a gate electrode structure that are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the electrode stack to expose sidewall surfaces of the interlayer insulation layer and the gate electrode structure, a gate dielectric layer disposed along a sidewall surface of the trench, the gate dielectric layer including a ferroelectric portion and a non-ferroelectric portion, and a channel layer disposed to adjacent to the gate dielectric layer. The ferroelectric portion is in contact with the gate electrode structure, and the non-ferroelectric portion is in contact with the interlayer insulation layer.

Abstract: A semiconductor device includes a substrate, a bit line conductive layer disposed on the substrate and extending in a first lateral direction substantially parallel to a surface of the substrate, first and second channel structures disposed on the bit line conductive layer to be spaced apart from each other in the first lateral direction, first and second gate dielectric layers disposed on side surfaces of the first and second channel structures over the substrate, first and second gate line conductive layers disposed on the first and second gate dielectric layers, respectively, the first and second gate line conductive layers common to the first and second channel structures, respectively, and extending in a second lateral direction perpendicular to the first lateral direction and substantially parallel to the surface of the substrate, and first and second storage node electrode layers disposed over the first and second channel structures, respectively.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a stack including a conductive pattern and an insulating pattern, a channel structure penetrating the stack, and a memory pattern between the conductive pattern and the channel structure. The memory pattern includes a blocking pattern, a tunnel pattern, a storage pattern, and a ferroelectric pattern.

Abstract: A method of providing information on a social networking service (SNS) activity to a chatroom, performed by a server, includes: providing an SNS for each of a plurality of anonymous profiles created to be interlinked with an account for an instant messaging service (IMS); receiving information on an SNS activity performed through a first anonymous profile selected corresponding to a chatroom of the IMS, among the plurality of anonymous profiles of a user participating in the chatroom; providing the information on the SNS activity performed through the first anonymous profile to the chatroom; receiving a request to change the profile of the user selected corresponding to the chatroom from the first anonymous profile to a second anonymous profile; receiving information on an SNS activity performed through the second anonymous profile; and providing the information on the SNS activity performed through the second anonymous profile to the chatroom.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a stack including a conductive pattern and an insulating pattern, a channel structure penetrating the stack, and a memory pattern between the conductive pattern and the channel structure. The memory pattern includes a blocking pattern, a tunnel pattern, a storage pattern, and a ferroelectric pattern.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an electrode stack disposed on the substrate, the electrode stack including an interlayer insulation layer and a gate electrode structure that are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the electrode stack to expose sidewall surfaces of the interlayer insulation layer and the gate electrode structure, a gate dielectric layer disposed along a sidewall surface of the trench, the gate dielectric layer including a ferroelectric portion and a non-ferroelectric portion, and a channel layer disposed to adjacent to the gate dielectric layer. The ferroelectric portion is in contact with the gate electrode structure, and the non-ferroelectric portion is in contact with the interlayer insulation layer.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a channel structure extending in a direction perpendicular to the substrate; a charge storage structure disposed to be in contact with the channel structure; and a cell electrode structure disposed to be in contact with the charge storage structure in a lateral direction, wherein the channel structure comprises a hole conduction layer and an electron conduction layer.

Abstract: A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.

Abstract: A method of displaying an interface for providing a social networking service (SNS) through an anonymous profile, performed by a user terminal, includes displaying a first list of at least one anonymous chatroom created by a user account for an instant messaging service (IMS) using a first region on a first page in an interface for the IMS, displaying a second list of at least one anonymous profile created to be interlinked with the user account using a first region on a second page in the interface for the IMS, and displaying, in response to an input of selecting any one anonymous profile in the second list, an interface for providing the SNS through the selected anonymous profile.

Abstract: A semiconductor device according to an embodiment includes a substrate, and a gate structure disposed over the substrate. The gate structure includes a hole pattern including a central axis extending in a direction perpendicular to a surface of the substrate. The gate structure includes a gate electrode layer and an interlayer insulation layer, which are alternately stacked along the central axis. The semiconductor device includes a ferroelectric layer disposed adjacent to a sidewall surface of the gate electrode layer inside the hole pattern, and a channel layer disposed adjacent to the ferroelectric layer inside the hole pattern. In this case, one of the gate electrode layer and the interlayer insulation layer protrudes toward the central axis of the hole pattern relative to the other one of the gate electrode layer and the interlayer insulation layer.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a cell electrode structure disposed on the substrate and including interlayer insulating layers and gate electrode layers that are alternately stacked, a trench penetrating the cell structure on the substrate, a charge storage structure disposed on a sidewall surface of the trench, and a channel structure disposed adjacent to the charge storage structure and extending in a direction parallel to the sidewall surface. The channel structure includes a separate hole conduction layer and an adjacent and separate electron conduction layer. A control channel layer disposed on a control dielectric layer is a portion of the electron conduction layer configured to electrically connect to the channel structure, and to the charge storage structure. A control dielectric layer and a charge barrier layer are discrete but contiguous from the control channel structure to the charge storage structure.

Abstract: A ferroelectric component includes a first electrode, a tunnel barrier layer disposed on the first electrode to include a ferroelectric material, a tunneling control layer disposed on the tunnel barrier layer to control a tunneling width of electric charges passing through the tunnel barrier layer, and a second electrode disposed on the tunneling control layer.

Abstract: A semiconductor device having a super junction and a method of manufacturing the semiconductor device capable of obtaining a high breakdown voltage are provided, whereby charge balance of the super junction is further accurately controlled in the semiconductor device that is implemented by an N-type pillar and a P-type pillar. The semiconductor device includes a semiconductor substrate; and a blocking layer including a first conductive type pillar and a second conductive type pillar that extend in a vertical direction on the semiconductor substrate and that are alternately arrayed in a horizontal direction, wherein, in the blocking layer, a density profile of a first conductive type dopant may be uniform in the horizontal direction, and the density profile of the first conductive type dopant may vary in the vertical direction.

Abstract: A method of displaying an interface for providing a social networking service (SNS) through an anonymous profile, performed by a user terminal, includes displaying a first list of at least one anonymous chatroom created by a user account for an instant messaging service (IMS) using a first region on a first page in an interface for the IMS, displaying a second list of at least one anonymous profile created to be interlinked with the user account using a first region on a second page in the interface for the IMS, and displaying, in response to an input of selecting any one anonymous profile in the second list, an interface for providing the SNS through the selected anonymous profile.

Abstract: A method of displaying an interface for providing a social networking service (SNS) through an anonymous profile, performed by a user terminal, includes displaying a first list of at least one anonymous chatroom created by a user account for an instant messaging service (IMS) using a first region on a first page in an interface for the IMS, displaying a second list of at least one anonymous profile created to be interlinked with the user account using a first region on a second page in the interface for the IMS, and displaying, in response to an input of selecting any one anonymous profile in the second list, an interface for providing the SNS through the selected anonymous profile.

Abstract: In a method, a stack structure including a plurality of first interlayer sacrificial layers and a plurality of second interlayer sacrificial layers that are alternately stacked is formed over a substrate. A trench penetrating the stack structure is formed. A channel layer covering a sidewall surface of the trench is formed. The plurality of first interlayer sacrificial layers are selectively removed to form a plurality of first recesses. The plurality of first recesses are filled with a conductive material to form a plurality of channel contact electrode layers. The plurality of second interlayer sacrificial layers are selectively removed to form a plurality of second recesses. A plurality of interfacial insulation layers, a plurality of ferroelectric layers and a plurality of gate electrode layers are formed in the plurality of second recesses.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.