Abstract: Disclosed herein is an apparatus for receiving data from memory. The apparatus receives a data signal and a clock signal output from memory and includes a Decision Feedback Equalizer (DFE) including two or more differential signal path units configured to determine and output an output value corresponding to the data signal. Each of the two or more differential signal path units may determine a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path units in such a way that they operate at different clocks, and may include an offset control unit configured to adjust an offset at an input stage and a feedback control unit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path units.

Abstract: Provided are a method for generating a summary and a system therefor. The method according to some embodiments may include calculating a likelihood loss for a summary model using a first text sample and a first summary sentence corresponding to the first text sample, calculating an unlikelihood loss for the summary model using a second text sample and the first summary sentence, the second text sample being a negative sample generated from the first text sample, and updating the summary model based on the likelihood loss and the unlikelihood loss.

Abstract: A battery includes an electrode assembly including a first electrode, a second electrode and a separator between the first electrode and the second electrode, the first electrode, the second electrode and the separator being wound around a winding axis to define a core and an outer peripheral surface. The first electrode and the second electrode include a first uncoated region and a second uncoated region along a winding direction, respectively, and an active material layer coating is absent in the first uncoated region and the second uncoated region. The battery further includes a housing receiving the electrode assembly through an opening formed at a bottom, a first current collector coupled to the first uncoated region and disposed within the housing, a cap covering the opening, a spacer interposed between the cap and the electrode assembly to fix the electrode assembly and seal the housing, and a terminal electrically connected to the second uncoated region.

Abstract: A battery includes an electrode assembly defining a core and an outer circumference by winding a first electrode, a second electrode, and a separator interposed therebetween around a winding center, each of the first electrode and the second electrode includes a first uncoated portion and a second uncoated portion on which an active material layer is not coated along the winding direction; a battery housing accommodating the electrode assembly through an opening formed on one side thereof; a cap including a venting portion, covering the opening, and electrically connected to the battery housing and the first uncoated portion; and a battery terminal penetrating one surface of the battery housing and electrically connected to the second uncoated portion.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on a winding axis to define a core and an outer circumference. The first electrode includes a first active material portion coated with an active material layer and a first uncoated portion not coated with an active material layer along a winding direction. At least a part of the first uncoated portion is defined as an electrode tab by itself. The first uncoated portion includes a first portion adjacent to the core of the electrode assembly, a second portion adjacent to the outer circumference of the electrode assembly, and a third portion interposed between the first portion and the second portion. The first portion or the second portion has a smaller height than the third portion in the winding axis direction.

Abstract: A battery includes an electrode assembly including a first uncoated region and a second uncoated region; a battery housing accommodating the electrode assembly and electrically connected to the second uncoated region; a cap to cover an open portion on bottom of the battery housing; a first electrode terminal passing through a partially closed portion of the battery housing and being electrically isolated from the battery housing; and a first current collector coupled to the first uncoated region and connected to the first electrode terminal.

Abstract: Provided are an electrode assembly, a battery, and a battery pack and vehicle including the same. An electrode assembly, in which a first electrode, a second electrode, and a separator interposed therebetween are wound about an axis to define a core and an outer circumferential surface. At least one of the first electrode and the second electrode includes, at a long side end portion, an uncoated portion exposed beyond the separator in a direction of the axis. At least a part of the uncoated portion is bent in a radial direction of the electrode assembly to define a bent surface region having overlapping layers of the uncoated portion. The bent surface region includes a welding target region having a number of the overlapping layers of the uncoated portion, and the welding target region extends along a radial direction of the electrode assembly.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on an axis to define a core and an outer circumference. The first electrode includes an uncoated portion at a long side end thereof and exposed out of the separator along a winding axis direction of the electrode assembly. A part of the uncoated portion is bent in a radial direction of the electrode assembly to form a bending surface region that includes overlapping layers of the uncoated portion, and in a partial region of the bending surface region, the number of stacked layers of the uncoated portion is 10 or more in the winding axis direction of the electrode assembly.

Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes a wiring substrate including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers and having a cavity penetrating through a portion of the plurality of insulating layers, a passive component disposed in the cavity and including an external electrode electrically connected to at least one of the plurality of wiring layers, and a bridge disposed on the passive component in the cavity and including one or more circuit layers electrically connected to the external electrode.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: A display device includes a substrate, a first conductive layer on the substrate, the first conductive layer including a data signal line, a first insulating layer on the first conductive layer, a semiconductor layer on the first insulating layer, the semiconductor layer including a first semiconductor pattern, a second insulating layer on the semiconductor layer, and a second conductive layer on the second insulating layer, the second conductive layer including a gate electrode disposed to overlap the first semiconductor pattern, a transistor first electrode disposed to overlap a part of the first semiconductor pattern, wherein the transistor first electrode is electrically connected to the data signal line through a contact hole that penetrates the first and second insulating layers, and a transistor second electrode disposed to overlap another part of the first semiconductor pattern.

Abstract: Disclosed are a method for inducing a prediction motion vector and an apparatus using the same. An image decoding method can include: a step of determining the information related to a plurality of spatial candidate prediction motion vectors from peripheral predicted blocks of a predicted target block; and a step of determining the information related to temporal candidate prediction motion vectors on the basis of the information related to the plurality of spatial candidate prediction motion vectors. Accordingly, the present invention can reduce complexity and can enhance coding efficiency when inducing the optimum prediction motion vector.

Abstract: An apparatus for embedding a sentence feature vector according to an embodiment includes a sentence acquisitor configured to acquire a first sentence and a second sentence, each including one or more words; a vector extractor configured to extract a first feature vector corresponding to the first sentence and a second feature vector corresponding to the second sentence by independently inputting each of the first sentence and the second sentence into a feature extraction network; and a vector compressor configured to compress the first feature vector and the second feature vector into a first compressed vector and a second compressed vector, respectively, by independently inputting each of the first feature vector and the second feature vector into a convolutional neural network (CNN)-based vector compression network.

Abstract: Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.

Abstract: [SUMMARY] A method of detecting a sequence-based intrusion by using a Database CAN (DBC) file, the method being performed by a computing device including a processor according to some exemplary embodiments of the present disclosure, includes: obtaining a first Controller Area Network (CAN) message generated from a CAN; determining the first CAN message as a first category among a plurality of categories based on a pre-stored DBC file; obtaining first predictive data from the first CAN message by using a pre-trained first neural network model, the pre-trained first neural network model corresponding to the first category and including a first hidden layer; and comparing the first predictive data and first actual data obtained based on the first CAN message to determine whether the first CAN message has an anomaly.

Abstract: An antenna module includes a wiring structure including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers; an antenna disposed on an upper surface of the wiring structure; a heat dissipation structure disposed around the antenna on the upper surface of the wiring structure; and an encapsulant disposed on the upper surface of the wiring structure and covering at least a portion of each of the antenna and the heat dissipation structure.

Abstract: Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.

Abstract: An antenna module includes a wiring structure including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers; an antenna disposed on an upper surface of the wiring structure; a heat dissipation structure disposed around the antenna on the upper surface of the wiring structure; and an encapsulant disposed on the upper surface of the wiring structure and covering at least a portion of each of the antenna and the heat dissipation structure.

Abstract: A printed circuit board includes a first insulating layer, a second insulating layer disposed on a lower surface of the first insulating layer, an electronic component embedded in the second insulating layer and at least partially in contact with the first insulating layer, a first wiring layer disposed on an upper surface of the first insulating layer, a second wiring layer disposed on a lower surface of the second insulating layer, and a first wiring via penetrating through the first and second insulating layers and connecting at least portions of the first and second wiring layers to each other.

Abstract: An antenna module includes a wiring structure including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers; an antenna disposed on an upper surface of the wiring structure; and an encapsulant disposed on the upper surface of the wiring structure and covering at least a portion of the antenna. An uppermost wiring layer of the plurality of wiring layers is connected to the antenna through a connection via of an uppermost via layer of the plurality of via layers. The connection via penetrates at least a portion of the encapsulant.