Abstract: Methods and systems for enhancing engagement between a purchaser and a manufacturer of an article. The system includes a web portal configured to elicit information from the purchaser including customer profile information and conversion preferences, wherein the web portal is configured to: i) affix a customer code embodying the profile information to a shipping container and ship the container to the purchaser; ii) receive indicia of the customer code from the purchaser following receipt of the shipped container; and iii) create an on-line account for the purchaser based on the indicia.

Abstract: In a described example, an apparatus includes a semiconductor substrate and at least two pillar bumps formed on an active surface of the semiconductor substrate, the at least two pillar bumps extending away from the active surface and having ends spaced from the semiconductor substrate with solder material at the ends of the at least two pillar bumps. At least one spacer is formed on the active surface of the semiconductor substrate, the at least one spacer extending a predetermined distance from the active surface of the semiconductor substrate. A package substrate has a die mount area on a first surface including portions receiving the ends of the at least two pillar bumps and receiving an end of the at least one spacer. Mold compound covers the semiconductor substrate, the at least two pillars, the at least one spacer, and at least a portion of the semiconductor substrate.

Abstract: A diffraction grating 1 includes a surface 12 having grooves 14 therein, each groove 14 providing a diffracting surface for light incident upon the diffracting surface. The grooves 14 are separated from each other by lands 20 upon the surface 12. The lands 20 are of predetermined varying width, whereby the diffractive efficiency of the grating 1 varies across the extent of the grating 1.

Abstract: Methods and systems for enhancing engagement between a purchaser and a manufacturer of an article. The system includes a web portal configured to elicit information from the purchaser including customer profile information and conversion preferences, wherein the web portal is configured to: i) affix a customer code embodying the profile information to a shipping container and ship the container to the purchaser; ii) receive indicia of the customer code from the purchaser following receipt of the shipped container; and iii) create an on-line account for the purchaser based on the indicia.

Abstract: Techniques and systems for storing and retrieving data storage devices of a data storage system are disclosed. In some embodiments, inventory holders are used to store data storage devices used by a data storage system. When data is to be transacted with the data storage devices, mobile drive units locate appropriate inventory holders and transport them to a device reading station, where an appropriate device retrieval unit transacts the data. After the data has been transacted, the data storage devices are returned to the appropriate inventory holders, and the inventory holders are placed by the mobile drive units in locations where they may be accessed in response to further data transactions.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes one or more computing resources and a memory controller coupled to a memory device. The memory controller determines a memory access request targets a given bank of multiple banks. An access history is updated for the given bank based on whether the memory access request hits on an open page within the given bank and a page hit rate for the given bank is determined. The memory controller sets an idle cycle limit based on the page hit rate. The idle cycle limit is a maximum amount of time the given bank will be held open before closing the given bank while the bank is idle. The idle cycle limit is based at least in part on a page hit rate for the bank.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory read requests have been sent to a memory device in a read mode of a data bus, the memory controller determines a threshold number of memory write requests to send to the memory device in an upcoming write mode is a number of outstanding memory write requests. Alternatively, the memory controller determines the threshold number of memory write requests to send to the memory device in an upcoming write mode is a maximum value of the number of outstanding memory write requests and a programmable value of the write burst length stored in a control register. Therefore, the write burst length is determined dynamically. Similarly, the read burst length is determined dynamically when the write mode ends.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses in a computing system are disclosed. In various embodiments, a computing system includes computing resources and a memory controller coupled to a memory device. The memory controller determines a memory request targets a given rank of multiple ranks. The memory controller determines a predicted latency for the given rank as an amount of time the pending queue in the memory controller for storing outstanding memory requests does not store any memory requests targeting the given rank. The memory controller determines the total bank latency as an amount of time for refreshing a number of banks which have not yet been refreshed in the given rank with per-bank refresh operations. If there are no pending requests targeting the given rank, each of the predicted latency and the total bank latency is used to select between per-bank and all-bank refresh operations.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. A computing system includes one or more clients for processing applications. A memory controller transfers traffic between the memory controller and two channels, each connected to a memory device. A client sends a 64-byte memory request with an indication specifying that there are two 32-byte requests targeting non-contiguous data within a same page. The memory controller generates two addresses, and sends a single command and the two addresses to two channels to simultaneously access non-contiguous data in a same page.

Abstract: A waveguide structure for a head up display in which a reflective output coupling structure is formed of a separate, but connected, component to a main waveguide. In a method of manufacture for such a waveguide the output coupling structure may be formed by depositing a material on a main waveguide, impressing the reflective structure into that material, and curing the material.

Abstract: A waveguide structure for a head up display in which a reflective output coupling structure is formed of a separate, but connected, component to a main waveguide. Light is coupled from the main waveguide to the output coupling structure by evanescent wave coupling. In a method of manufacture for such a waveguide the output coupling structure is attached to the main waveguide using an optical feedback technique.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes a computing resource and a memory controller coupled to a memory device. The computing resource selectively generates a hint that includes a target address of a memory request generated by the processor. The hint is sent outside the primary communication fabric to the memory controller. The hint conditionally triggers a data access in the memory device. When no page in a bank targeted by the hint is open, the memory controller processes the hint by opening a target page of the hint without retrieving data. The memory controller drops the hint if there are other pending requests that target the same page or the target page is already open.

Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.

Abstract: Certain aspects of the technology disclosed herein include measuring and reporting the unit planar area incident radiant flux striking multiple planes at known, determined angles of tilt from the horizontal and pre-determined angles of azimuthal orientation corresponding to that of an associated solar power generating apparatus which employs a single axis or two axis photovoltaic module tracking design.

Abstract: Systems, apparatuses, and methods for identifying response data arriving out-of-order from two different memory types are disclosed. A computing system includes one or more clients for processing applications. A memory channel transfers memory traffic between a memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a given point in time when read data is to be scheduled to arrive on the memory bus from memory. The memory controller associates a unique identifier with the given point in time. The memory controller identifies a given command associated with the arriving read data based on the given point in time.

Abstract: A pressure equalization valve assembly may include a valve body forming fluid chamber configured to receive pressurized fluid from a fluid pressure source, a first port configured for sealed communication with a first vehicle tire, and a second port configured for sealed communication with a second vehicle tire; a first one-way valve disposed in the valve body between the fluid chamber and the first port so as to allow one-way fluid communication from the fluid chamber to the first port when the first one-way valve opens; a second one-way valve disposed in the valve body between the fluid chamber and the second port so as to allow one-way fluid communication from the fluid chamber to the second port when the second one-way valve opens; and a two-way valve disposed in the valve body between the first port and the second port so as to allow two-way fluid communication between the first port and the second port when the two-way valve opens.

Abstract: Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set.

Abstract: A wafer-level chip-scale package (WLCSP) includes an integrated circuit (IC) chip, and die bonding pads with a redistribution layer (RDL) having multiple via structures located directly below the footprint of a solder ball placed on the bonding pad. The via structures electrically connect the solder ball to a top metal layer of the IC chip. The RDL may extend beyond the solder ball's footprint and have additional vias that connect to the top metal layer, including vias located under and connected to other solder balls. The bonding pads have a low R-on resistance and are not susceptible to thermal-induced cracking.

Abstract: Certain aspects of the technology disclosed herein include measuring and reporting the unit planar area incident radiant flux striking multiple planes at known, determined angles of tilt from the horizontal and pre-determined angles of azimuthal orientation corresponding to that of an associated solar power generating apparatus which employs a single axis or two axis photovoltaic module tracking design.

Abstract: Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set.