Patents by Inventor James Fitzpatrick

James Fitzpatrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Search for an optimized read voltage
    Patent number: 11244729
    Abstract: A memory device to search for a voltage optimized to read a group of memory cells. In response to a read command, the memory device measures first signal and noise characteristics of the memory cells by reading the memory cells at first test voltages. Based on the first signal and noise characteristics, the memory device may determine that the optimized read voltage is outside of a range of the first test voltages. In response, the memory device determines, based on the first signal and noise characteristics, an estimate of the optimized read voltage, and measures second signal and noise characteristics by reading at second test voltages configured around the estimate. The optimized read voltage can be computed based at least in part on the second signal and noise characteristics. The memory device retrieves data from the memory cells using the optimized read voltage.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Patrick Robert Khayat, James Fitzpatrick, AbdelHakim S. Alhussien, Sivagnanam Parthasarathy
  • Determine bit error count based on signal and noise characteristics centered at an optimized read voltage
    Patent number: 11238953
    Abstract: A memory device to estimate a bit error count of data retrievable from a group of memory cells. For example, the memory device has a group of memory cells programmed to store a predetermined number of bits per memory cells to be read at a plurality of first voltages. The memory device determines a plurality of calibrated read voltages corresponding to the plurality of first voltages respectively, based on first signal and noise characteristics of the group of memory cells. The first signal and noise characteristics are used to compute second signal and noise characteristics of the group of memory cells for the calibrated read voltages. The second signal and noise characteristics are used in an empirical formula to compute an estimate of the bit error count of data retrievable from the group of memory cells using the calibrated read voltages.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Patrick Robert Khayat, Sivagnanam Parthasarathy, James Fitzpatrick
  • Memory system performance enhancements using measured signal and noise characteristics of memory cells
    Patent number: 11237726
    Abstract: A memory sub-system configured to improve performance using signal and noise characteristics of memory cells measured during the execution of a command in a memory component. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing the command in the memory component. A processing device separate from the memory component transmits the command to the memory component, and receives and processes the signal and noise characteristics to identify an attribute about the memory component. Subsequently, an operation related to data stored in the memory component can be performed based on the attribute.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien, Violante Moschiano
  • Track charge loss based on signal and noise characteristics of memory cells collected in calibration operations
    Patent number: 11227666
    Abstract: A memory sub-system to track charge loss in memory cells and shifts of voltages optimized to read the memory cells. For example, a memory device can measure signal and noise characteristics of a group of memory cells to calculate an optimized read voltage of the group of memory cells. The memory sub-system having the memory device can determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage. The memory sub-system tracks changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: January 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • DETERMINE SIGNAL AND NOISE CHARACTERISTICS CENTERED AT AN OPTIMIZED READ VOLTAGE
    Publication number: 20220013186
    Abstract: A memory device to estimate signal and noise characteristics of a group of memory cells in response to a command identifying the group of memory cells. For example, the memory device measures first signal and noise characteristics of the group of memory cells based on first test voltages, compute using the first signal and noise characteristics an optimized read voltage of the group of memory cells, and estimate, using the first signal and noise characteristics, second signal and noise characteristics of the group of memory cells, where the second signal and noise characteristics are based on second test voltages that are centered at the optimized read voltage of the group of memory cells.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Patrick Robert Khayat, Sivagnanam Parthasarathy, James Fitzpatrick
  • Adaptive and/or iterative operations in executing a read command to retrieve data from memory cells
    Patent number: 11221800
    Abstract: A memory sub-system configured to adaptively and/or iteratively determine sub-operations of executing a read command to retrieve data from memory cells. For example, after receiving the read command from a processing device of a memory sub-system, a memory device starts an atomic operation of executing the read command in the memory device. The memory device can have one or more groups of memory cells formed on an integrated circuit die and a calibration circuit configured to measure signal and noise characteristics of memory cells in the memory device. During the atomic operation, the calibration circuit generates outputs, based on which a read manager of the memory sub-system identifies sub-operations to be performed in the atomic operation and/or decides to end the atomic operation.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Two-Layer Code with Low Parity Cost for Memory Sub-Systems
    Publication number: 20210407612
    Abstract: A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Inventors: Sanjay Subbarao, James Fitzpatrick
  • Read disturb mitigation based on signal and noise characteristics of memory cells collected for read calibration
    Patent number: 11205495
    Abstract: A memory device to perform a read disturb mitigation operation. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine a margin of read disturb accumulated in the group of memory cells. Subsequently, the memory device can identify the group of memory cells for the read disturb mitigation operation based on the margin of read disturb and a predetermined threshold.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Patrick Robert Khayat, James Fitzpatrick, AbdelHakim S. Alhussien, Sivagnanam Parthasarathy
  • Optimization of soft bit windows based on signal and noise characteristics of memory cells
    Patent number: 11200959
    Abstract: A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Determine signal and noise characteristics centered at an optimized read voltage
    Patent number: 11177013
    Abstract: A memory device to estimate signal and noise characteristics of a group of memory cells in response to a command identifying the group of memory cells. For example, the memory device measures first signal and noise characteristics of the group of memory cells based on first test voltages, compute using the first signal and noise characteristics an optimized read voltage of the group of memory cells, and estimate, using the first signal and noise characteristics, second signal and noise characteristics of the group of memory cells, where the second signal and noise characteristics are based on second test voltages that are centered at the optimized read voltage of the group of memory cells.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Patrick Robert Khayat, Sivagnanam Parthasarathy, James Fitzpatrick
  • Detection of an Incorrectly Located Read Voltage
    Publication number: 20210350868
    Abstract: A memory device to program a group of memory cells to store multiple bits per memory cell. Each bit per memory cell in the group from a page. After determining a plurality of read voltages of the group of memory cells, the memory device can read the multiple pages of the group using the plurality of read voltages. For each respective page in the multiple pages, the memory device can determine a count of first memory cells in the respective page that have threshold voltages higher than a highest read voltage, among the plurality of read voltages, used to read the respective page. The count of the first memory cells can be compared with a predetermined range of a fraction of memory cells in the respective page to evaluate the plurality of read voltages (e.g., whether any of the read voltages is in a wrong voltage range).
    Type: Application
    Filed: May 6, 2021
    Publication date: November 11, 2021
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • DETERMINE SIGNAL AND NOISE CHARACTERISTICS CENTERED AT AN OPTIMIZED READ VOLTAGE
    Publication number: 20210350866
    Abstract: A memory device to estimate signal and noise characteristics of a group of memory cells in response to a command identifying the group of memory cells. For example, the memory device measures first signal and noise characteristics of the group of memory cells based on first test voltages, compute using the first signal and noise characteristics an optimized read voltage of the group of memory cells, and estimate, using the first signal and noise characteristics, second signal and noise characteristics of the group of memory cells, where the second signal and noise characteristics are based on second test voltages that are centered at the optimized read voltage of the group of memory cells.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 11, 2021
    Inventors: Patrick Robert Khayat, Sivagnanam Parthasarathy, James Fitzpatrick
  • Intelligent Proactive Responses to Operations to Read Data from Memory Cells
    Publication number: 20210350869
    Abstract: A memory device to generate intelligent, proactive responses to a read command. For example, signal and noise characteristics of a group of memory cells in a memory device are measured to determine a read voltage. An action is identified based on evaluation of the quality of data retrievable using the read voltage from the group of memory cells. While a response indicating the action is provided responsive to the command, the memory device can initiate the action proactively before a subsequent command, following the response, is received.
    Type: Application
    Filed: June 11, 2021
    Publication date: November 11, 2021
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • READ SOFT BITS THROUGH BOOSTED MODULATION FOLLOWING READING HARD BITS
    Publication number: 20210350857
    Abstract: A memory sub-system configured to read soft bit data by adjusting the read voltage applied to read hard bit data from memory cells. For example, in response to a read command identifying a group of memory cells, a memory device is to: read the group of memory cells using a first voltage to generate hard bit data indicating statuses of the memory cells subjected to the first voltage; change (e.g., through boosted modulation) the first voltage, currently being applied to the group of memory cells, to a second voltage and then to a third voltage; reading the group of memory cells at the second voltage and at the third voltage to generate soft bit data (e.g., via an exclusive or (XOR) of the results of reading the group of memory cells at the second voltage and at the third voltage).
    Type: Application
    Filed: May 7, 2020
    Publication date: November 11, 2021
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • IMPROVED READING OF SOFT BITS AND HARD BITS FROM MEMORY CELLS
    Publication number: 20210350856
    Abstract: A memory sub-system configured to execute a read command of a first type using a combine process to read soft bit data and hard bit data from memory cells. For example, a memory device is to: measure signal and noise characteristics of memory cells for the read command; calculate, based on the characteristics, an optimized voltage and two adjacent voltages that have offsets of a same amount from the optimized voltage; read the memory cells for hard bit data using the optimized voltage and for soft bit data using the two adjacent voltages; and transmit, to the processing device, a response including the hard bit data. The soft bit data can be selectively transmitted based on a classification determined from the characteristics. When a read command of a second type is executed, soft bit data is not read; and/or the signal and noise characteristics are not measured.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 11, 2021
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • COMPUTE AN OPTIMIZED READ VOLTAGE
    Publication number: 20210350867
    Abstract: A memory device to determine a voltage optimized to read a group of memory cells by reading the group of memory cells at a plurality of test voltages, computing bit counts at the test voltages respectively, and computing count differences in the bit counts for pairs of adjacent voltages in the test voltages. When a smallest one in the count differences is found at a side of a distribution of the count differences according to voltage, the memory device is configured to determine a location of an optimized read voltage, based on a ratio between a first count difference and a second count difference, where the first count difference is the smallest in the count differences, and the second count difference is closest in voltage to the first count difference.
    Type: Application
    Filed: April 23, 2021
    Publication date: November 11, 2021
    Inventors: Patrick Robert Khayat, James Fitzpatrick, AbdelHakim S. Alhussien, Sivagnanam Parthasarathy
  • DETERMINE BIT ERROR COUNT BASED ON SIGNAL AND NOISE CHARACTERISTICS CENTERED AT AN OPTIMIZED READ VOLTAGE
    Publication number: 20210350872
    Abstract: A memory device to estimate a bit error count of data retrievable from a group of memory cells. For example, the memory device has a group of memory cells programmed to store a predetermined number of bits per memory cells to be read at a plurality of first voltages. The memory device determines a plurality of calibrated read voltages corresponding to the plurality of first voltages respectively, based on first signal and noise characteristics of the group of memory cells. The first signal and noise characteristics are used to compute second signal and noise characteristics of the group of memory cells for the calibrated read voltages. The second signal and noise characteristics are used in an empirical formula to compute an estimate of the bit error count of data retrievable from the group of memory cells using the calibrated read voltages.
    Type: Application
    Filed: May 7, 2020
    Publication date: November 11, 2021
    Inventors: Patrick Robert Khayat, Sivagnanam Parthasarathy, James Fitzpatrick
  • Two-layer code with low parity cost for memory sub-systems
    Patent number: 11164652
    Abstract: A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Subbarao, James Fitzpatrick
  • Multi-Level Cell Programming Using Optimized Multiphase Mapping with Balanced Gray Code
    Publication number: 20210327504
    Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 21, 2021
    Inventors: Mostafa EL GAMAL, Niranjay RAVINDRAN, James FITZPATRICK
  • Iterative read calibration enhanced according to patterns of shifts in read voltages
    Patent number: 11152073
    Abstract: A memory sub-system configured to use first values of a plurality of optimized read voltages to perform a first read calibration, which determines second values of the plurality of optimized read voltages. A plurality of shifts, from the first values to the second values respectively, can be computed for the plurality of optimized read voltages respectively. After recognizing a pattern in the plurality of shifts that are computed for the plurality of voltages respectively, the memory sub-system can control and/or initiate a second read calibration based on the recognized pattern in the shifts.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James Fitzpatrick, Sivagnanam Parthasarathy, Patrick Robert Khayat, AbdelHakim S. Alhussien