Patents by Inventor James Fitzpatrick

James Fitzpatrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-Level Cell Programming Using Optimized Multiphase Mapping With Balanced Gray Code
    Publication number: 20200327933
    Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Inventors: Mostafa EL GAMAL, Niranjay RAVINDRAN, James FITZPATRICK
  • Mapping for Multi-State Programming of Memory Devices
    Publication number: 20200320009
    Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.
    Type: Application
    Filed: June 18, 2020
    Publication date: October 8, 2020
    Inventors: Bernie RUB, Mostafa EL GAMAL, Niranjay RAVINDRAN, Richard David BARNDT, Henry CHIN, Ravi J. KUMAR, James FITZPATRICK
  • Advanced stationary sealing concepts for axial retention of ceramic matrix composite shrouds
    Patent number: 10794204
    Abstract: In one aspect, the present disclosure is directed to a gas turbine sealing assembly that includes a first static gas turbine wall and a second static gas turbine wall. A seal is disposed between the first static gas turbine wall and the second static gas turbine wall. The seal includes a shield wall constructed from a first material that includes a first shield wall portion and a second shield wall portion. A spring constructed from a second material includes a first spring portion and a second spring portion. The first shield wall portion is adjacent to the first spring portion, and the second shield wall portion is adjacent to the second spring portion.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: October 6, 2020
    Assignee: General Electric Company
    Inventors: Dylan James Fitzpatrick, David Scott Stapleton, Jonathan David Baldiga, Christopher Paul Tura
  • MULTI-PHASED PROGRAMMING WITH BALANCED GRAY CODING
    Publication number: 20200286562
    Abstract: Disclosed are systems and methods for providing multi-phased programming with balanced Gray coding. A method includes programming, in a first phase, a first portion of data into memory cells of a flash memory in a first-level cell mode. The method also includes retaining, in a cache, at least a subset of the data. The method also includes regenerating the data from at least the cache, wherein the regenerated data includes a second portion of the data. The method also includes programming, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode. The mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode, and a width of each state distribution in the first-level cell mode may be narrowed.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 10, 2020
    Inventors: Sergey Anatolievich GOROBETS, Xinmiao ZHANG, James FITZPATRICK
  • MODULAR FOLDING TABLE WITH COLLAPSIBLE LEGS
    Publication number: 20200268143
    Abstract: A portable modular folding table can include a substantially flat tabletop having three or more tabletop sections, hinges coupled to the tabletop sections, and collapsible legs that are modular and separate from the tabletop. The tabletop can have a width and a length that is at least twice as large as the width, and the tabletop sections are coupled to and foldable onto each other to reduce the length of the tabletop by less than half when the tabletop is reduced from a fully extended configuration to a fully compacted configuration. Each of the collapsible legs can be adjustable to multiple different heights and can have multiple tabletop support points. The tabletop can rest atop the tabletop support points when the tabletop is in a fully extended configuration and the tabletop can be separated from and stored alongside the collapsible legs when the tabletop is in a fully compacted configuration.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 27, 2020
    Inventor: Joseph James Fitzpatrick
  • Multi-level cell programming using optimized multiphase mapping with balanced Gray code
    Patent number: 10734071
    Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mostafa El Gamal, Niranjay Ravindran, James Fitzpatrick
  • Mapping for multi-state programming of memory devices
    Patent number: 10705966
    Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 7, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Bernie Rub, Mostafa El Gamal, Niranjay Ravindran, Richard David Barndt, Henry Chin, Ravi J. Kumar, James Fitzpatrick
  • MULTI-LEVEL CELL PROGRAMMING USING OPTIMIZED MULTIPHASE MAPPING WITH BALANCED GRAY CODE
    Publication number: 20200194063
    Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Mostafa EL GAMAL, Niranjay RAVINDRAN, James FITZPATRICK
  • MAPPING FOR MULTI-STATE PROGRAMMING OF MEMORY DEVICES
    Publication number: 20200192807
    Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Bernie RUB, Mostafa EL GAMAL, Niranjay RAVINDRAN, Richard David BARNDT, Henry CHIN, Ravi J. KUMAR, James FITZPATRICK
  • WEAR LEVELING WITH WEAR-BASED ATTACK DETECTION FOR NON-VOLATILE MEMORY
    Publication number: 20200105354
    Abstract: Apparatuses, systems, and methods are disclosed for wear leveling for non-volatile memory. An apparatus may include one or more non-volatile memory elements, and a controller. A controller may perform a wear-leveling process for one or more non-volatile memory elements, by periodically updating a logical-to-physical mapping and moving data based on the updated mapping. A controller may detect a wear-based attack for one or more non-volatile memory elements. A controller may change a wear-leveling process in response to detecting a wear-based attack.
    Type: Application
    Filed: September 29, 2018
    Publication date: April 2, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: DANIEL HELMICK, AMIR GHOLAMIPOUR, JAMES FITZPATRICK
  • Ceramic matrix composite ring shroud retention methods-finger seals with stepped shroud interface
    Patent number: 10443417
    Abstract: The present disclosure is directed to a retention assembly for a gas turbine component including a first and a second gas turbine wall respectively defining a first and a second surface. A retainer, positioned between the first and the second surfaces, includes a flange, which contacts the first surface. A plurality of fingers extends outwardly from the flange. A first finger portion extends away from the first turbine wall toward the second wall. A second finger portion connected to the first finger portion extends substantially parallel to the flange. The second finger portion of a first finger of the plurality of fingers is positioned in a first slot defined in the second surface. The second finger portion of a second finger of the plurality of fingers adjacent to the first finger is positioned on the second surface adjacent to the first slot.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: October 15, 2019
    Assignee: General Electric Company
    Inventors: Dylan James Fitzpatrick, Christopher Paul Tura
  • Advanced stationary sealing cooled cross-section for axial retention of ceramic matrix composite shrouds
    Patent number: 10273821
    Abstract: In one aspect, the present subject matter is directed to a gas turbine sealing assembly that includes a first static gas turbine wall and a second static gas turbine wall. A seal is disposed between the first static gas turbine wall and the second static gas turbine wall. The seal includes a first seal layer defining a first seal layer aperture extending therethrough. A second seal layer defines an elongated slot extending therethrough. The elongated slot includes a first end and a second end. A third seal layer defines a third seal layer aperture extending therethrough. The second seal layer is positioned between the first seal layer and the third seal layer such that the first seal layer aperture is in fluid communication with the first end and the third seal layer aperture is in fluid communication with the second end.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: April 30, 2019
    Assignee: General Electric Company
    Inventor: Dylan James Fitzpatrick
  • Variable-term error metrics adjustment
    Patent number: 10228990
    Abstract: Systems, methods and/or devices are used to adjust error metrics for a memory portion of non-volatile memory in a storage device. In one aspect, a first write and a first read are performed on the memory portion. In accordance with results of the first read, a first error metric value for the memory portion is determined. In accordance with a determination that the first error metric value exceeds a first threshold value, an entry for the memory portion is added to a table. After the first write, when a second write to the memory portion is performed, it is determined whether the entry for the memory portion is present in the table. In accordance with a determination that the entry for the memory portion is present in the table, the second write uses a first error adjustment characteristic that is determined in accordance with the first error metric value.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: March 12, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yiwei Song, Nian Niles Yang, James Fitzpatrick
  • Apparatus and method for controlling an audio/video connection in a device
    Patent number: 10194202
    Abstract: An apparatus and method for controlling an audio/video connection in a device is described. The method includes entering a first state in response to a user input, the first state powering a portion of circuits, detecting the presence of a signal, the signal to be output from the device for display on a display device, and entering a second state if the presence of the signal is detected, powering circuits for outputting the received signal. The apparatus includes a standby circuit, receiving a user input placing the apparatus into a first state, a receiving circuit detecting the presence of a signal in the first state and providing a signal to place the apparatus in a second state if the signal is detected, and a processing circuit being operational in the second state, the signal processing circuit outputting the signal for display on a display device in the second state.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: January 29, 2019
    Assignee: INTERDIGITAL CE PATENT HOLDINGS
    Inventor: John James Fitzpatrick
  • Paired metablocks in non-volatile storage device
    Patent number: 10126970
    Abstract: Systems, methods and/or devices are used to pair metablocks in a non-volatile storage device. In one aspect, a method of data organization of a memory device includes, writing data to and reading data from respective metablocks in a set of metablocks. The method further includes while performing said writing and reading: (1) accessing one or more management data structures in controller memory, identifying two or more metablock pairs; (2) accessing and updating metablock status information indicating which metablocks of the set of metablocks are closed, free and open; and (3) accessing and updating a valid count, corresponding to a number of sub-block memory units having valid data for each of a plurality of metablocks in the set of metablocks.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: November 13, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Amir Shaharabany, Hadas Oshinsky, Yacov Duzly, James Fitzpatrick
  • Attachment assembly and gas turbine engine with attachment assembly
    Patent number: 10119424
    Abstract: An attachment assembly for attaching a center structure to an outer structure at least partially circumscribing the center structure, the attachment assembly having a bushing provided within the center structure or the outer structure, the bushing defining a first through passage, a bushing adapter slidably mounted within the first through passage and defining a second through passage, a threaded passage provided on the other of the center structure or the outer structure and a bolt passing through the first through passage and the second through passage and threaded into the threaded passage.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: November 6, 2018
    Assignee: General Electric Company
    Inventors: Apostolos Pavlos Karafillis, Christopher Dale Mathias, Kyle Earl Roland Henry, Dylan James Fitzpatrick, Dennis Robert Jonassen, Paul W. Donahue
  • Ceramic matrix composite ring shroud retention methods-wiggle strip spring seal
    Patent number: 10094244
    Abstract: The present disclosure is directed to a retention assembly for a stationary gas turbine component. The retention assembly includes a first stationary gas turbine wall having a first surface. A retention boss extends outwardly from the first surface. The retention assembly includes a second stationary gas turbine wall having a second surface. A retainer is positioned between the first and the second surfaces. The retainer includes a base wall positioned adjacent to the retention boss. A first sidewall extends outwardly from the base wall, and a second sidewall extends outwardly from the base wall. A first arm extends outwardly from the first sidewall, and a second arm extends outwardly from the second sidewall. Each of the first arm and the second arm includes a plurality of convolutions. At least one of the plurality of convolutions is in contact with the second surface.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: October 9, 2018
    Assignee: General Electric Company
    Inventors: Dylan James Fitzpatrick, Christopher Paul Tura
  • Data management in a storage system
    Patent number: 10049037
    Abstract: A storage system, and a method of data management in the storage system, with non-volatile memory device characteristics determined during an inspection of non-volatile memory devices before a runtime operation of a storage device in the storage system including: a controller in the storage system: a drive-level control unit configured for an update of operational capabilities based on the non-volatile memory device characteristics during the runtime operation of the storage device and for a group of the non-volatile memory devices based on the operational capabilities; and a memory control unit, coupled to the drive-level control unit, the memory control unit configured to receive the operational capabilities for control of the non-volatile memory devices.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: August 14, 2018
    Assignee: SanDisk Enterprise IP LLC
    Inventors: John Scaramuzzo, Bernardo Rub, Robert W. Ellis, James Fitzpatrick
  • Ceramic matrix composite ring shroud retention methods-CMC pin-head
    Patent number: 9945257
    Abstract: The present disclosure is directed to a retention assembly for a stationary gas turbine component. A first stationary gas turbine wall defines a first wall cavity and a second stationary gas turbine wall constructed from a ceramic matrix composite defines a second wall cavity. A pin shaft constructed from a first material includes a first shaft end and a second shaft end. A pin head constructed from the ceramic matrix composite includes a first pin head end and a second pin head end. The pin head defines a pin head cavity extending inward from the first pin head end. The first shaft end is positioned in the first wall cavity, and the second shaft end is positioned in the pin head cavity. The second pin head end is positioned in the second wall cavity. The first material is different from the ceramic matrix composite.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: April 17, 2018
    Assignee: General Electric Company
    Inventors: Dylan James Fitzpatrick, Christopher Paul Tura
  • System for thermally isolating a turbine shroud
    Patent number: 9945242
    Abstract: In one aspect the present subject matter is directed to a system for thermally isolating a turbine shroud of a turbine shroud assembly. The system includes a shroud support having an inner surface and a turbine shroud that is connected to the shroud support. The turbine shroud includes a hot side surface that is radially spaced from a back side surface. At least a portion of the back side surface is oriented towards the inner surface of the shroud support. The system further includes a coating that is disposed along the back side surface of the turbine shroud. The coating regulates heat transfer from the turbine shroud to the shroud support or other hardware that may surround or be adjacent to the turbine shroud.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: April 17, 2018
    Assignee: General Electric Company
    Inventors: Christopher Paul Tura, Dylan James Fitzpatrick