Abstract: The various embodiments described herein include methods, systems, and devices for optimizing media read times. In one aspect, a method is performed at a device at a storage device with one or more processors and memory coupled to the one or more processors. The method includes: (i) predicting a read frequency for particular data; (ii) based on the predicted read frequency, determining one or more preferred storage locations within the memory; and (iii) storing the particular data in a preferred storage location of the one or more preferred storage locations.

Abstract: The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention (DR) performance. The CT memory may be 3D memory that uses a charge storage layer for storing charge may have unique data retention behavior. Memory blocks using a charge storage layer may be dynamically detected and reconditioned and re-programmed to improve memory characteristics, such as data retention. The reconditioning may include a dedicated erase cycle for a block that improves the data retention.

Abstract: A three dimensional nonvolatile memory system includes a sensing unit configured to sense bit line current and/or voltage for bit lines of a plurality of separately-selectable portions of a block and to compare respective results with a reference and an adjustment unit configured to individually modify operating parameters for one or more of the plurality of separately-selectable portions in response to the comparing of respective results with the reference.

Abstract: Systems, methods and/or devices are used to pair metablocks in a non-volatile storage device. In one aspect, a method of data organization of a memory device includes, writing data to and reading data from respective metablocks in a set of metablocks. The method further includes while performing said writing and reading: (1) accessing one or more management data structures in controller memory, identifying two or more metablock pairs; (2) accessing and updating metablock status information indicating which metablocks of the set of metablocks are closed, free and open; and (3) accessing and updating a valid count, corresponding to a number of sub-block memory units having valid data for each of a plurality of metablocks in the set of metablocks.

Abstract: Systems, methods and/or devices are used to enable dynamic erase block grouping. In one aspect, the method includes (1) maintaining metadata for each erase block of a plurality of erase blocks in a data storage system, wherein a respective metadata for a respective erase block includes one or more characteristics of the respective erase block, (2) allocating a set of erase blocks, of the plurality of erase blocks, as unassociated erase blocks, (3) selecting two or more unassociated erase blocks in accordance with characteristics of the unassociated erase blocks so as to select unassociated erase blocks with similar characteristics, and (4) grouping the two or more unassociated erase blocks with similar characteristics to form a super block.

Abstract: Systems, methods and/or devices are used to adjust error metrics for a memory portion of non-volatile memory in a storage device. In one aspect, a first write and a first read are performed on the memory portion. In accordance with results of the first read, a first error metric value for the memory portion is determined. In accordance with a determination that the first error metric value exceeds a first threshold value, an entry for the memory portion is added to a table. After the first write, when a second write to the memory portion is performed, it is determined whether the entry for the memory portion is present in the table. In accordance with a determination that the entry for the memory portion is present in the table, the second write uses a first error adjustment characteristic that is determined in accordance with the first error metric value.

Abstract: Systems, methods and/or devices are used to enable garbage collection of a sub-block of an individually erasable block of a storage medium in a storage device. In one aspect, the method includes determining a first trigger parameter in accordance with one or more operating conditions of a first sub-block of an erase block in the storage medium, and determining a second trigger parameter in accordance with one or more operating conditions of a second sub-block of the erase block in the storage medium. In accordance with a determination that the first trigger parameter meets a first vulnerability criterion, garbage collection of the first sub-block is enabled. Furthermore, in accordance with a determination that the second trigger parameter meets a second vulnerability criterion, garbage collection of the second sub-block is enabled.

Abstract: In one aspect, the present disclosure is directed to a gas turbine sealing assembly that includes a first static gas turbine wall and a second static gas turbine wall. A seal is disposed between the first static gas turbine wall and the second static gas turbine wall. The seal includes a shield wall constructed from a first material that includes a first shield wall portion and a second shield wall portion. A spring constructed from a second material includes a first spring portion and a second spring portion. The first shield wall portion is adjacent to the first spring portion, and the second shield wall portion is adjacent to the second spring portion.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention (DR) performance. The CT memory may be 3D memory that uses a charge storage layer for storing charge may have unique data retention behavior. Memory blocks using a charge storage layer may be dynamically detected and reconditioned and re-programmed to improve memory characteristics, such as data retention. The reconditioning may include a dedicated erase cycle for a block that improves the data retention.

Abstract: The present disclosure is directed to a retention assembly for a stationary gas turbine component. A first stationary gas turbine wall defines a first wall cavity and a second stationary gas turbine wall constructed from a ceramic matrix composite defines a second wall cavity. A pin shaft constructed from a first material includes a first shaft end and a second shaft end. A pin head constructed from the ceramic matrix composite includes a first pin head end and a second pin head end. The pin head defines a pin head cavity extending inward from the first pin head end. The first shaft end is positioned in the first wall cavity, and the second shaft end is positioned in the pin head cavity. The second pin head end is positioned in the second wall cavity. The first material is different from the ceramic matrix composite.

Abstract: In a nonvolatile memory block that contains separately-selectable sets of NAND strings, a bit line current sensing unit is configured to sense bit line current for a separately-selectable set of NAND strings of the block. A bit line voltage adjustment unit is configured to apply a first and second bit line voltages to separately-selectable sets of NAND strings that have bit line currents greater and less than the minimum current respectively, the second bit line voltage being greater than the first bit line voltage.

Abstract: A three dimensional nonvolatile memory system includes a sensing unit configured to sense bit line current and/or voltage for bit lines of a plurality of separately-selectable portions of a block and to compare respective results with a reference and an adjustment unit configured to individually modify operating parameters for one or more of the plurality of separately-selectable portions in response to the comparing of respective results with the reference.

Abstract: The present disclosure is directed to a retention assembly for a gas turbine component including a first and a second gas turbine wall respectively defining a first and a second surface. A retainer, positioned between the first and the second surfaces, includes a flange, which contacts the first surface. A plurality of fingers extends outwardly from the flange. A first finger portion extends away from the first turbine wall toward the second wall. A second finger portion connected to the first finger portion extends substantially parallel to the flange. The second finger portion of a first finger of the plurality of fingers is positioned in a first slot defined in the second surface. The second finger portion of a second finger of the plurality of fingers adjacent to the first finger is positioned on the second surface adjacent to the first slot.

Abstract: The present disclosure is directed to a retention assembly for a stationary gas turbine component. The retention assembly includes a first stationary gas turbine wall having a first surface. A retention boss extends outwardly from the first surface. The retention assembly includes a second stationary gas turbine wall having a second surface. A retainer is positioned between the first and the second surfaces. The retainer includes a base wall positioned adjacent to the retention boss. A first sidewall extends outwardly from the base wall, and a second sidewall extends outwardly from the base wall. A first arm extends outwardly from the first sidewall, and a second arm extends outwardly from the second sidewall. Each of the first arm and the second arm includes a plurality of convolutions. At least one of the plurality of convolutions is in contact with the second surface.

Abstract: In one aspect, the present subject matter is directed to a gas turbine sealing assembly that includes a first static gas turbine wall and a second static gas turbine wall. A seal is disposed between the first static gas turbine wall and the second static gas turbine wall. The seal includes a first seal layer defining a first seal layer aperture extending therethrough. A second seal layer defines an elongated slot extending therethrough. The elongated slot includes a first end and a second end. A third seal layer defines a third seal layer aperture extending therethrough. The second seal layer is positioned between the first seal layer and the third seal layer such that the first seal layer aperture is in fluid communication with the first end and the third seal layer aperture is in fluid communication with the second end.

Abstract: A storage control system, and a method of operation thereof, including: a power-down module for powering off a memory sub-system; a decay estimation module, coupled to the power-down module, for estimating a power-off decay rate upon the memory sub-system powered up, the power-off decay rate is for indicating how much data in the memory sub-system has decayed while the memory sub-system has been powered down; and a recycle module, coupled to the decay estimation module, for recycling an erase block for data retention based on the power-off decay rate.

Abstract: An apparatus and method for controlling an audio/video connection in a device is described. The method includes entering a first state in response to a user input, the first state powering a portion of circuits, detecting the presence of a signal, the signal to be output from the device for display on a display device, and entering a second state if the presence of the signal is detected, powering circuits for outputting the received signal. The apparatus includes a standby circuit, receiving a user input placing the apparatus into a first state, a receiving circuit detecting the presence of a signal in the first state and providing a signal to place the apparatus in a second state if the signal is detected, and a processing circuit being operational in the second state, the signal processing circuit outputting the signal for display on a display device in the second state.

Abstract: Systems, methods and/or devices are used to enable dynamic erase block grouping. In one aspect, the method includes (1) maintaining metadata for each erase block of a plurality of erase blocks in a data storage system, wherein a respective metadata for a respective erase block includes one or more characteristics of the respective erase block, (2) allocating a set of erase blocks, of the plurality of erase blocks, as unassociated erase blocks, (3) selecting two or more unassociated erase blocks in accordance with characteristics of the unassociated erase blocks so as to select unassociated erase blocks with similar characteristics, and (4) grouping the two or more unassociated erase blocks with similar characteristics to form a super block.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable adaptive erasure in a storage device. The method includes performing a plurality of memory operations including read operations and respective erase operations on portions of one or more non-volatile memory devices specified by the read operations and respective erase operations, where the respective erase operations are performed using a first set of erase parameters that has been established as a current set of erase parameters prior to performing the respective erase operations. The method includes, in accordance with each erase operation of at least a subset of the respective erase operations, updating one or more erase statistics that correspond to performance of multiple erase operations. The method includes, in accordance with a comparison of the erase statistics with an erasure performance threshold, establishing a second set of erase parameters as the current set of erase parameters.