Abstract: Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the unselected cells. The unselected cells share bit lines with the selected cells and may also share word lines. Preventing erase disturb may also include applying voltages to the select transistors that prevent the erase voltage from passing from the shared bit lines to the channels of the unselected cells. The voltages decrease from the bit lines to the unselected memory cells and may prevent GIDL generation. Current consumption is kept low.

Abstract: A three dimensional NAND device includes a common vertical channel and electrically isolated control gate electrodes on different lateral sides of the channel in each device level to form different lateral portions of a memory cell in each device level. Dielectric separator structures are located between and electrically isolate the control gate electrodes. The lateral portions of the memory cell in each device level may be electrically isolated by at least one of doping ungated portions of the channel adjacent to the separator structures or storing electrons in the separator structure.

Abstract: A memory device includes a plurality of memory cells arranged in a string substantially perpendicular to the major surface of the substrate in a plurality of device levels, at least one first select gate electrode located between the major surface of the substrate and the plurality of memory cells, at least one second select gate electrode located above the plurality of memory cells, a semiconductor channel having a portion that extends vertically along a direction perpendicular to the major surface, a first memory film contacting a first side of the semiconductor channel, and a second memory film contacting a second side of the semiconductor channel. The second memory film is electrically isolated from the first memory film, and is located at a same level as the first memory film.

Abstract: A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: In a fabrication process for reversible resistance-switching memory cells, a bottom electrode layer is coated with nano-particles. The nano-particles are used to etch the bottom electrode layer, forming multiple narrow, spaced apart bottom electrode structures for each memory cell. A resistance-switching material is then deposited between and above the bottom electrode structures, followed by a top electrode layer. Or, insulation is deposited between and above the bottom electrode structures, followed by planarizing and a wet etch to expose top surfaces of the bottom electrode structures, then deposition of the resistance-switching material and the top electrode layer. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

Abstract: A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer.

Abstract: A memory device includes a plurality of memory cells arranged in a string substantially perpendicular to the major surface of the substrate in a plurality of device levels, at least one first select gate electrode located between the major surface of the substrate and the plurality of memory cells, at least one second select gate electrode located above the plurality of memory cells, a semiconductor channel having a portion that extends vertically along a direction perpendicular to the major surface, a first memory film contacting a first side of the semiconductor channel, and a second memory film contacting a second side of the semiconductor channel. The second memory film is electrically isolated from the first memory film, and is located at a same level as the first memory film.

Abstract: A three dimensional NAND device includes a common vertical channel and electrically isolated control gate electrodes on different lateral sides of the channel in each device level to form different lateral portions of a memory cell in each device level. Dielectric separator structures are located between and electrically isolate the control gate electrodes. The lateral portions of the memory cell in each device level may be electrically isolated by at least one of doping ungated portions of the channel adjacent to the separator structures or storing electrons in the separator structure.

Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.

Abstract: A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.

Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.

Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.

Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.

Abstract: A process for forming reversible resistance-switching memory cells having resistance-switching nano-particles which provide a reduced contact area to top and bottom electrodes of the memory cells, thereby limiting a peak current. Recesses are formed in a layered semiconductor material above the bottom electrodes, and one or more coatings of nano-particles are applied. The nano-particles self-assemble in the recesses so that they are positioned in a controlled manner. A top electrode material is then deposited. In one approach, the recesses are formed by spaced-apart trenches, and the nano-particles self-assemble along the spaced-apart trenches. In another approach, the recesses for each resistance-switching memory cell are separate from one another, and the resistance-switching memory cells are pillar-shaped. The coatings can be provided in one layer, or in multiple layers which are separated by an insulation layer.

Abstract: A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer.

Abstract: A process for forming reversible resistance-switching memory cells having resistance-switching nano-particles which provide a reduced contact area to top and bottom electrodes of the memory cells, thereby limiting a peak current. Recesses are formed in a layered semiconductor material above the bottom electrodes, and one or more coatings of nano-particles are applied. The nano-particles self-assemble in the recesses so that they are positioned in a controlled manner. A top electrode material is then deposited. In one approach, the recesses are formed by spaced-apart trenches, and the nano-particles self-assemble along the spaced-apart trenches. In another approach, the recesses for each resistance-switching memory cell are separate from one another, and the resistance-switching memory cells are pillar-shaped. The coatings can be provided in one layer, or in multiple layers which are separated by an insulation layer.