Patents by Inventor James K. Kai
James K. Kai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8710481Abstract: A non-volatile memory device includes a plurality of non-volatile memory cells. Each of the non-volatile memory cells includes a first electrode, a diode steering element, a storage element located in series with the diode steering element, a second electrode, and a nano-rail electrode having a width of 15 nm or less.Type: GrantFiled: January 23, 2012Date of Patent: April 29, 2014Assignee: SanDisk 3D LLCInventors: James K. Kai, Henry Chien, George Matamis, Vinod R. Purayath
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Publication number: 20140008804Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.Type: ApplicationFiled: September 10, 2013Publication date: January 9, 2014Applicant: SanDisk Technologies, Inc.Inventors: Vinod R. Purayath, James K. Kai, Jayavel Pachamuthu, Jarrett Jun Liang, George Matamis
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Publication number: 20130334587Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.Type: ApplicationFiled: July 22, 2013Publication date: December 19, 2013Applicant: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, Tuan Pham, Hiroyuki Kinoshita, Yuan Zhang, Henry Chin, James K. Kai, Takashi W. Orimoto, George Matamis, Henry Chien
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Patent number: 8575000Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.Type: GrantFiled: July 19, 2011Date of Patent: November 5, 2013Assignee: SanDisk Technologies, Inc.Inventors: Vinod R. Purayath, James K. Kai, Jayavel Pachamuthu, Jarrett Jun Liang, George Matamis
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Publication number: 20130187114Abstract: A non-volatile memory device includes a plurality of non-volatile memory cells. Each of the non-volatile memory cells includes a first electrode, a diode steering element, a storage element located in series with the diode steering element, a second electrode, and a nano-rail electrode having a width of 15 nm or less.Type: ApplicationFiled: January 23, 2012Publication date: July 25, 2013Applicant: SanDisk 3D LLCInventors: James K. Kai, Henry Chien, George Matamis, Vinod R. Purayath
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Patent number: 8492224Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.Type: GrantFiled: June 17, 2011Date of Patent: July 23, 2013Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, Tuan Pham, Hiroyuki Kinoshita, Yuan Zhang, Henry Chin, James K. Kai, Takashi W. Orimoto, George Matamis, Henry Chien
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Publication number: 20130105881Abstract: A non-volatile memory fabrication process includes the formation of a complete memory cell layer stack before isolation region formation. The memory cell layer stack includes an additional place holding control gate layer. After forming the layer stack columns, the additional control gate layer will be incorporated between an overlying control gate layer and underlying intermediate dielectric layer. The additional control gate layer is self-aligned to isolation regions between columns while the overlying control gate layer is etched into lines for contact to the additional control gate layer. In one embodiment, the placeholder control gate layer facilitates a contact point to the overlying control gate layer such that contact between the control gate layers and the charge storage layer is not required for select gate formation.Type: ApplicationFiled: October 5, 2012Publication date: May 2, 2013Inventors: James K. Kai, Vinod R. Purayath, George Matamis, Nima Mokhlesi, Cuong Trinh
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Patent number: 8383479Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.Type: GrantFiled: July 20, 2010Date of Patent: February 26, 2013Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, James K. Kai, Masaaki Higashitani, Takashi Orimoto, George Matamis, Henry Chien
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Publication number: 20130020708Abstract: A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.Type: ApplicationFiled: July 19, 2011Publication date: January 24, 2013Applicant: SanDisk Technologies, IncInventors: Vinod R. Purayath, James K. Kai, Jayavel Pachamuthu, Jarrett Jun Liang, George Matamis
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Patent number: 8207036Abstract: A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.Type: GrantFiled: September 30, 2008Date of Patent: June 26, 2012Assignee: SanDisk Technologies Inc.Inventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, Henry Chien, James K. Kai
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Patent number: 8105867Abstract: A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.Type: GrantFiled: May 19, 2009Date of Patent: January 31, 2012Assignee: SanDisk 3D LLCInventors: George Matamis, Henry Chien, James K Kai, Takashi Orimoto, Vinod R Purayath, Er-Xuan Ping, Roy E Scheuerlein
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Publication number: 20110309426Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.Type: ApplicationFiled: June 17, 2011Publication date: December 22, 2011Inventors: Vinod Robert Purayath, Tuan Pham, Hiroyuki Kinoshita, Yuan Zhang, Henry Chin, James K. Kai, Takashi W. Orimoto, George Matamis, Henry Chien
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Patent number: 7919809Abstract: A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.Type: GrantFiled: July 9, 2008Date of Patent: April 5, 2011Assignee: SanDisk CorporationInventors: Dana Lee, Henry Chin, James K. Kai, Takashi Whitney Orimoto, Vinod R. Purayath, George Matamis
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Patent number: 7915124Abstract: A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.Type: GrantFiled: July 9, 2008Date of Patent: March 29, 2011Assignee: Sandisk CorporationInventors: James K. Kai, Dana Lee, Takashi Whitney Orimoto, Vinod R. Purayath, George Matamis, Henry Chin
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Publication number: 20110020992Abstract: Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating.Type: ApplicationFiled: July 20, 2010Publication date: January 27, 2011Inventors: Vinod Robert Purayath, James K. Kai, Masaaki Higashitani, Takashi Orimoto, George Matamis, Henry Chien
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Publication number: 20100124813Abstract: A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.Type: ApplicationFiled: May 19, 2009Publication date: May 20, 2010Inventors: George Matamis, Henry Chien, James K. Kai, Takashi Orimoto, Vinod R Purayath, Er-Xuan Ping, Roy E. Scheuerlein
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Publication number: 20100081267Abstract: A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Inventors: Vinod Robert Purayath, George Matamis, Takashi Orimoto, Henry Chien, James K. Kai
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Publication number: 20100009503Abstract: A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.Type: ApplicationFiled: July 9, 2008Publication date: January 14, 2010Inventors: James K. Kai, Dana Lee, Takashi Whitney Orimoto, Vinod R. Purayath, George Matamis, Henry Chin
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Publication number: 20100006915Abstract: A memory system is disclosed that includes a set of non-volatile storage elements. A given memory cell has a dielectric cap above the floating gate. In one embodiment, the dielectric cap resides between the floating gate and a conformal IPD layer. The dielectric cap reduces the leakage current between the floating gate and a control gate. The dielectric cap achieves this reduction by reducing the strength of the electric field at the top of the floating gate, which is where the electric field would be strongest without the dielectric cap for a floating gate having a narrow stem.Type: ApplicationFiled: July 9, 2008Publication date: January 14, 2010Inventors: Dana Lee, Henry Chin, James K. Kai, Takashi Whitney Orimoto, Vinod R. Purayath, George Matamis
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Patent number: 6670265Abstract: An integrated circuit wafer and a manufacturing process for etching low K spin-on dielectrics such as HSQ in a High Density Plasma etch reactor utilizes roof and wall temperature to improve across-the-wafer uniformity, and a mixture of C4F8 and C2F6 etch gases to eliminate mid via etch stop and to maintain selectivity over underlying etch-stop layers.Type: GrantFiled: June 4, 1999Date of Patent: December 30, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, James K. Kai, Angela T. Hui