Abstract: A method for forming a metal interconnect structure in a semiconductor device with the elimination of via poisoning during trench mask formation employs a CVD organic BARC that isolates the low k dielectric film. The CVD organic BARC is deposited over the low k dielectric film and in the via hole. Once the trench mask has been formed on the CVD organic BARC, the CVD organic BARC may be removed in the same process as the photoresist of the trench mask layer. A properly formed trench will have been created since the via poisoning and resist scumming were substantially eliminated by the presence of the CVD organic BARC.

Abstract: A cleaving tool provides pressurized gas to the edge of a substrate to cleave the substrate at a selected interface. A substrate, such as a bonded substrate, is loaded into the cleaving tool, and two halves of the tool are brought together to apply a selected pressure to the substrate. A compliant pad of selected elastic resistance provides support to the substrate while allowing the substrate to expand during the cleaving process. Bringing the two halves of the tool together also compresses an edge seal against the perimeter of the substrate. A thin tube connected to a high-pressure gas source extends through the edge seal and provides a burst of gas to separate the substrate into at least two sheets. In a further embodiment, the perimeter of the substrate is struck with an edge prior to applying the gas pressure.

Abstract: A method of manufacturing a semiconductor device includes forming a second barrier layer over a first level, forming a first dielectric layer over the second barrier layer, forming a second dielectric layer over the first dielectric layer, etching the first and second dielectric layers to form an opening through the first dielectric layer and the second dielectric layer, depositing an organic fill material in the opening and removing a portion of the organic fill material before etching the second dielectric layer to form a trench. The organic fill material can then be completely removed and the second barrier layer is etched to expose the first level. The trench and a via are then filled with a conductive material to form a feature.

Abstract: A cleaving tool provides pressurized gas to the edge of a substrate in combination with a sharpened edge to cleave the substrate at a selected interface. The edge of the tool is tapped against the perimeter of a substrate, such as a bonded substrate, and a burst of gas pressure is then applied at approximately the point of contact with the edge of the tool. The combination of mechanical force and gas pressure separates the substrate into two halves at a selected interface, such as a weakened layer in a donor wafer.

Abstract: An integrated circuit wafer and a manufacturing process for etching low K spin-on dielectrics such as HSQ in a High Density Plasma etch reactor utilizes roof and wall temperature to improve across-the-wafer uniformity, and a mixture of C4F8 and C2F6 etch gases to eliminate mid via etch stop and to maintain selectivity over underlying etch-stop layers.

Abstract: A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.

Abstract: A cleaving tool provides pressurized gas to the edge of a substrate in combination with a sharpened edge to cleave the substrate at a selected interface. The edge of the tool is tapped against the perimeter of a substrate, such as a bonded substrate, and a burst of gas pressure is then applied at approximately the point of contact with the edge of the tool. The combination of mechanical force and gas pressure separates the substrate into two halves at a selected interface, such as a weakened layer in a donor wafer.

Abstract: A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.

Abstract: An in-situ etching process for creating local interconnects in a semiconductor device includes using a single etching tool to: etch through a masked dielectric layer to a stop layer using a mixture of C4F8/CH3F/Ar gasses; etch away the mask layer using a mixture of O2/Ar gasses; and etch through the stop layer using a mixture of CH3F/O2 gasses. The semiconductor device is not removed from the etching tool between the different etchings. The method then includes depositing conductive material to form local interconnects within the openings that were etched.

Abstract: A cleaving tool provides pressurized gas to the edge of a substrate in combination with a sharpened edge to cleave the substrate at a selected interface. The edge of the tool is tapped against the perimeter of a substrate, such as a bonded substrate, and a burst of gas pressure is then applied at approximately the point of contact with the edge of the tool. The combination of mechanical force and gas pressure separates the substrate into two halves at a selected interface, such as a weakened layer in a donor wafer.

Abstract: A cleaving tool provides pressurized gas to the edge of a substrate to cleave the substrate at a selected interface. A substrate, such as a bonded substrate, is loaded into the cleaving tool, and two halves of the tool are brought together to apply a selected pressure to the substrate. A compliant pad of selected elastic resistance provides support to the substrate while allowing the substrate to expand during the cleaving process. Bringing the two halves of the tool together also compresses an edge seal against the perimeter of the substrate. A thin tube connected to a high-pressure gas source extends through the edge seal and provides a burst of gas to separate the substrate into at least two sheets. In a further embodiment, the perimeter of the substrate is struck with an edge prior to applying the gas pressure.

Abstract: A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating material and the oxide layer to form the wiring trough. The partial etching step includes the steps of spin coating photoresist on top of the anti-reflective coating material, exposing the photoresist through a mask containing a pattern of the wiring trough, developing the photoresist to expose portions of the anti-reflective coating material, dry etching the exposed portions of the anti-reflective coating material to expose portions of the oxide layer, and wet etching the exposed portions of the oxide layer to form the wiring trough.

Abstract: An in-situ etching process for creating local interconnects in a semiconductor device includes using one etching tool to: etch through an organic, or inorganic BARC layer using O.sub.2 gas, or C.sub.2 F.sub.6 /O.sub.2 gases, respectively; a masked dielectric layer to a stop layer using a mixture of C.sub.4 F.sub.8, CH.sub.3 F and argon (Ar) gasses; etch away the mask layer using a mixture of O.sub.2 and Ar gasses; and, etch through the stop layer using a mixture of CH.sub.3 F gas and O.sub.2 gas. Remaining portions of the BARC layer, whether organic or inorganic, are also removed during the in-situ etching process using appropriate gases. The method then includes depositing conductive material within the openings that were etched to form local interconnects.

Abstract: A method of forming a via in a interlevel dielectric of a semiconductor device wherein the via has a fluted sidewall. A semiconductor substrate is provided having a first conductive layer formed thereon. A dielectric layer is then formed on the first conductive layer. A photoresist layer is deposited on a dielectric layer and a contact opening is formed in the photoresist layer to expose a contact region of the dielectric layer. A first etch step is performed to remove portions of the dielectric layer proximal to the contact region to form a first stage of the fluted via. The first stage includes a first sidewall stage extending from an upper surface of the dielectric layer at an angle less than 50.degree.. The first stage of the fluted via exterds a first lateral distance which is greater than a lateral dimension of the contact opening. A second etch step is then performed to further remove portions of the dielectric layer to form a second stage of the fluted via.

Abstract: A method of forming a via in a interlevel dielectric of a semiconductor device wherein the via has a fluted sidewall. A semiconductor substrate is provided having a first conductive layer formed thereon. A dielectric layer is then formed on the first conductive layer. A photoresist layer is deposited on a dielectric layer and a contact opening is formed in the photoresist layer to expose a contact region of the dielectric layer. A first etch step is performed to remove portions of the dielectric layer proximal to the contact region to form a first stage of the fluted via. The first stage includes a first sidewall stage extending from an upper surface of the dielectric layer at an angle less than 50.degree.. The first stage of the fluted via extends a first lateral distance which is greater than a lateral dimension of the contact opening. A second etch step is then performed to further remove portions of the dielectric layer to form a second stage of the fluted via.