Patents by Inventor James Pan

James Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8648174
    Abstract: The present invention is directed to novel polypeptide, designated in the present application as “UCP4” (SEQ ID NO: 1), having homology to certain human uncoupling proteins (“UCPs”) and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention, and methods for producing the polypeptides of the present invention.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: February 11, 2014
    Assignee: Genentech, Inc.
    Inventors: Sean Adams, James Pan, Alan Zhong
  • Patent number: 8628777
    Abstract: The present invention is directed to novel polypeptides having homology to the IL-1-like family of proteins and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention, and methods for producing the polypeptides of the present invention.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: January 14, 2014
    Assignee: Genentech, Inc.
    Inventors: Audrey Goddard, Guohua James Pan
  • Patent number: 8541840
    Abstract: A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: September 24, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: James Pan
  • Publication number: 20130244412
    Abstract: A method of fabricating a semiconductor device having a transistor with a metal gate electrode and a gate dielectric layer includes forming a protective layer on the gate dielectric layer and forming a metal gate electrode over the protective layer. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 19, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: James Pan, John Pellerin
  • Patent number: 8445975
    Abstract: A semiconductor device has a substrate, a gate dielectric layer, and a metal gate electrode on the gate dielectric layer. The gate dielectric layer includes an oxide layer having a dielectric constant (k) greater than 4, and silicon concentrated at interfaces of the oxide layer with the substrate and with the metal gate electrode. A method of fabricating a semiconductor device includes forming a removable gate over a substrate with a gate dielectric layer between the removable gate and the substrate, forming a dielectric layer over the substrate and exposing an upper surface of the removable gate, removing the removable gate leaving an opening in the dielectric layer, forming a protective layer on the gate dielectric layer and lining the opening, and forming a metal gate electrode in the opening. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: May 21, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James Pan, John Pellerin
  • Publication number: 20130064827
    Abstract: The present invention is directed to novel polypeptides having sequence identity with IL-17, IL-17 receptors and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention. Further provided herein are methods for treating degenerative cartilaginous disorders and other inflammatory diseases.
    Type: Application
    Filed: August 23, 2012
    Publication date: March 14, 2013
    Inventors: Jian Chen, Ellen Filvaroff, Sherman Fong, Dorothy French, Audrey Goddard, Paul J. Godowski, J. Christopher Grimaldi, Austin L. Gumey, Kenneth J. Hillan, Sarah G. Hymowitz, Hanzhong Li, James Pan, Melissa A. Starovasnik, Daniel Tumas, Menno Van Lookeren, Richard Vandlen, Colin K. Watanabe, P. Mickey Williams, William I. Wood, Daniel G. Yansura
  • Patent number: 8329538
    Abstract: A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: December 11, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, James J. Murphy
  • Publication number: 20120291932
    Abstract: The present invention is about an oval or asymmetric wheel design for luggage bags. The wheel is in an ellipsoidal configuration. Suspension, cushion, or elastic devices are installed in the oval wheels. These devices, when compressed by the weight of the luggage bag, store energy. When the luggage bag is shifted in the subsequent phase of the motion by the traveler, the energy in the devices is released from the cushion, and pushes the luggage toward the intended direction.
    Type: Application
    Filed: May 22, 2011
    Publication date: November 22, 2012
    Inventor: James Pan
  • Publication number: 20120292676
    Abstract: The present invention is for a fast optic nonvolatile memory cell (FONM) that operates with a speed >1000000 times faster than the commercially available FLASH memory. The information (or charges) can be entered into the FONM cell by switching on a built-in laser or LED (Light Emitting Diode). Excited by the lights, and driven by electric fields, the regions of low carrier lifetimes thermally generate excess electrons or positive charges to fill the storage gaps or interfaces. To detect the stored information, two BJTs (Bipolar Junction Transistors) are arranged in a mirrored configuration—with alternative regions of high or low carrier lifetimes and bandgap energies. By comparing the BJT “fly-back” characteristics a voltage difference can be detected as a signal of whether the information is stored or not stored.
    Type: Application
    Filed: May 21, 2011
    Publication date: November 22, 2012
    Inventor: James Pan
  • Patent number: 8313927
    Abstract: The present invention is directed to a novel polypeptide, designated in the present application as “UCP4” (SEQ ID NO: 1), having homology to certain human uncoupling proteins (“UCPs”) and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention, and methods for producing the polypeptides of the present invention.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: November 20, 2012
    Assignee: Genentech, Inc.
    Inventors: Sean Adams, James Pan, Alan Zhong
  • Publication number: 20120280293
    Abstract: In accordance with an embodiment, a method of forming a semiconductor structure can include forming a source region of a first conductivity type in a well region of a second conductivity type within a semiconductor region, and forming a first diffusion barrier region disposed between the source region and the well region. The method can include forming a heavy body region of the second conductivity type in the well region and forming a second diffusion bather region having a portion on a side of the heavy body region with a thickness different than a thickness of a portion on a bottom portion of the heavy body region. The method can also include forming a gate electrode, and forming a dielectric insulating the gate electrode from the semiconductor region.
    Type: Application
    Filed: July 16, 2012
    Publication date: November 8, 2012
    Inventor: James Pan
  • Publication number: 20120280312
    Abstract: In one embodiment, an apparatus can include a trench extending into a semiconductor region of a first conductivity type, an electrode disposed in the trench, and a source region of the first conductivity type abutting a sidewall of the trench. The apparatus can include a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode where the second conductivity type is opposite the first conductivity type. The apparatus can also include a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench, and a third well region of the first conductivity type disposed between the first well region and the second well region.
    Type: Application
    Filed: July 19, 2012
    Publication date: November 8, 2012
    Inventor: James Pan
  • Publication number: 20120273875
    Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.
    Type: Application
    Filed: April 27, 2011
    Publication date: November 1, 2012
    Inventors: Joseph A. Yedinak, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Hamza Yilmaz, James Pan, Rodney S. Ridley
  • Publication number: 20120273916
    Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.
    Type: Application
    Filed: April 27, 2011
    Publication date: November 1, 2012
    Inventors: Joseph A. Yedinak, Christopher L. Rexer, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Hamza Yilmaz, Chongman Yun, Dwayne S. Reichl, James Pan, Rodney S. Ridley, SR., Harold Heidenreich
  • Publication number: 20120273884
    Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.
    Type: Application
    Filed: April 27, 2011
    Publication date: November 1, 2012
    Inventors: Joseph A. Yedinak, Christopher L. Rexer, Mark L. Rinehimer, Praveen Muraleedharan Shenoy, Jaegil Lee, Hamza Yilmaz, Chongman Yun, Dwayne S. Reichl, James Pan, Rodney S. Ridley, SR., Harold Heidenreich
  • Patent number: 8278686
    Abstract: A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: October 2, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, Qi Wang
  • Patent number: 8278702
    Abstract: A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: October 2, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, Scott L. Hunt, Dean E. Probst, Hossein Paravi
  • Patent number: 8273703
    Abstract: The present invention is directed to novel polypeptides having sequence identity with IL-17, IL-17 receptors and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention. Further provided herein are methods for treating degenerative cartilaginous disorders and other inflammatory diseases.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: September 25, 2012
    Assignee: Genentech, Inc.
    Inventors: Jian Chen, Ellen Filvaroff, Sherman Fong, Dorothy French, Audrey Goddard, Paul J. Godowski, J. Christopher Grimaldi, Austin L. Gumey, Kenneth J. Hillan, Sarah G. Hymowitz, Hanzhong Li, James Pan, Melissa A. Starovasnik, Daniel Tumas, Menno Van Lookeren, Richard Vandlen, Colin K. Watanabe, P. Mickey Williams, William I. Wood, Daniel G. Yansura
  • Patent number: 8253194
    Abstract: A semiconductor structure comprises a drift region of a first conductivity type in a semiconductor region. A well region of a second conductivity type is over the drift region. A source region of the first conductivity type is in an upper portion of the well region. A heavy body region of the second conductivity type extends in the well region. The heavy body region has a higher doping concentration than the well region. A first diffusion barrier region at least partially surrounds the heavy body region. A gate electrode is insulated from the semiconductor region by a gate dielectric.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: August 28, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventor: James Pan
  • Publication number: 20120178163
    Abstract: The present invention is directed to novel polypeptides having homology to members of the tumor necrosis factor receptor family and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptides molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 12, 2012
    Inventors: Audrey Goddard, James Pan, Minhong Yan