Patents by Inventor James Pan

James Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120064073
    Abstract: The present invention is directed to novel polypeptides having sequence identity with IL-17, IL-17 receptors and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention. Further provided herein are methods for treating degenerative cartilaginous disorders and other inflammatory diseases.
    Type: Application
    Filed: October 10, 2011
    Publication date: March 15, 2012
    Inventors: Jian Chen, Ellen Fllvaroff, Sherman Fong, Dorothy French, Audrey Goddard, Paul J. Godowski, J. Christopher Grimaldi, Austin L. Gurney, Kenneth J. Hillan, Sarah G. Hymowitz, Hanzhong Li, James Pan, Melissa A. Starovasnik, Daniel Tumas, Menno Van Lookeren, Richard Vandlen, Colin K. Watanabe, P. Mickey Williams, William I. Wood, Daniel G. Yansura
  • Publication number: 20120058909
    Abstract: The present invention is directed to novel polypeptides having sequence identity with IL-17, IL-17 receptors and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention. Further provided herein are methods for treating degenerative cartilaginous disorders and other inflammatory diseases.
    Type: Application
    Filed: October 10, 2011
    Publication date: March 8, 2012
    Inventors: Jian Chen, Elleri Filvaroff, Sherman Fong, Dorothy French, Audrey Goddard, Paul J. Godowski, J. Christopher Grimaldi, Austin L. Gurney, Kenneth J. Hilian, Sarah G. Hymowitz, Hanzhong Li, James Pan, Melissa A. Starovasnik, Daniel Tumas, Menno Van Lookeren, Richard Vandlen, Colin K. Watanabe, P. Mickey Williams, William I. Wood, Daniel G. Yansura
  • Publication number: 20120049196
    Abstract: A semiconductor device has a substrate, a gate dielectric layer, and a metal gate electrode on the gate dielectric layer. The gate dielectric layer includes an oxide layer having a dielectric constant (k) greater than 4, and silicon concentrated at interfaces of the oxide layer with the substrate and with the metal gate electrode. A method of fabricating a semiconductor device includes forming a removable gate over a substrate with a gate dielectric layer between the removable gate and the substrate, forming a dielectric layer over the substrate and exposing an upper surface of the removable gate, removing the removable gate leaving an opening in the dielectric layer, forming a protective layer on the gate dielectric layer and lining the opening, and forming a metal gate electrode in the opening. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.
    Type: Application
    Filed: November 7, 2011
    Publication date: March 1, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: James Pan, John Pellerin
  • Publication number: 20120041176
    Abstract: The present invention is directed to novel polypeptides having homology to certain human uncoupling proteins (“UCPs”) and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention, and methods for producing the polypeptides of the present invention.
    Type: Application
    Filed: September 19, 2011
    Publication date: February 16, 2012
    Applicant: GENENTECH, INC.
    Inventors: Sean Adams, James Pan, Alan Zhong
  • Patent number: 8097500
    Abstract: In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating an n-type metal-oxide-semiconductor device using a gate first process, and fabricating a p-type metal-oxide-semiconductor device using a gate last process.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: January 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Eduard A. Cartier, Changhwan Choi, Elizabeth A. Duch, Bruce B. Doris, Young-Hee Kim, Vijay Narayanan, James Pan, Vamsi K. Paruchuri
  • Patent number: 8084795
    Abstract: The CMOS field effect transistors, used in microprocessors and other digital VLSI circuits, face major challenges such as thin gate dielectrics leakage and scaling limits, severe short channel effects, limited performance improvement with scaling, complicated fabrication process with added special techniques, and surface mobility degradation. This disclosure proposes a new CMOS-compatible optoelectronic transistor. The current is much higher than the MOS transistors, due to the high carrier mobility with bulk transportation. The optoelectronic transistors are scalable to the sub-nanometer ranges without short channel effects. It is also suitable for low power applications and ULSI circuits. The new transistor consists of a laser or LED diode as drain or source, and a photo sensor diode (avalanche photo diode) as source or drain.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: December 27, 2011
    Inventor: James Pan
  • Patent number: 8067229
    Abstract: The present invention is directed to novel polypeptides having homology to certain human uncoupling proteins (“UCPs”) and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention, and methods for producing the polypeptides of the present invention.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: November 29, 2011
    Assignee: Genentech, Inc.
    Inventors: Sean Adams, James Pan, Alan Zhong
  • Patent number: 8053849
    Abstract: Thin effective gate oxide thickness with reduced leakage for replacement metal gate transistors is achieved by forming a protective layer between the gate oxide layer and metal gate electrode, thereby reducing stress. Embodiments include forming a protective layer of amorphous carbon containing metal carbides decreasing in concentration from the metal gate electrode toward the gate oxide layer across the protective layer. Embodiments of methodology include removing the removable gate, depositing a layer of amorphous carbon on the gate oxide layer, forming the metal gate electrode and then heating at an elevated temperature to diffuse metal from the metal gate electrode into the amorphous carbon layer, thereby forming the metal carbides. Embodiments also include metal gate transistors with a gate oxide layer having a high dielectric constant and silicon concentrated at the interfaces with the metal gate electrode and substrate.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: November 8, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James Pan, John Pellerin
  • Publication number: 20110263086
    Abstract: A method of forming a field effect transistor (FET) includes forming a carbon-containing region over a substrate. An epitaxial layer is formed over the carbon-containing region. The epitaxial layer has a lower doping concentration than the substrate. A body region of a first conductivity type is formed in the epitaxial layer. The epitaxial layer is of a second conductivity type and forms a p-n junction with the body region. Gate electrodes are formed adjacent to but insulated from the body regions. Source regions of the second conductivity type are formed in the body regions. The source regions form p-n junctions with the body regions.
    Type: Application
    Filed: July 8, 2011
    Publication date: October 27, 2011
    Applicant: Fairchild Semicondutor Corporation
    Inventor: James Pan
  • Patent number: 8034342
    Abstract: The present invention is directed to novel polypeptides having sequence identity with IL-17, IL-17 receptors and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention. Further provided herein are methods for treating degenerative cartilaginous disorders and other inflammatory diseases.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: October 11, 2011
    Assignee: Genentech, Inc.
    Inventors: Jian Chen, Ellen Filvaroff, Sherman Fong, Dorothy French, Audrey Goddard, Paul J. Godowski, J. Christopher Grimaldi, Austin L. Gurney, Kenneth J. Hillan, Sarah G. Hymowitz, Hanzhong Li, James Pan, Melissa A. Starovasnik, Daniel Tumas, Menno Van Lookeren, Richard Vandlen, Colin K. Watanabe, P. Mickey Williams, William I. Wood, Daniel G. Yansura
  • Publication number: 20110244641
    Abstract: A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.
    Type: Application
    Filed: April 8, 2011
    Publication date: October 6, 2011
    Inventors: James Pan, James J. Murphy
  • Publication number: 20110215377
    Abstract: A vertically-conducting planar-gate field effect transistor includes a silicon region of a first conductivity type, a silicon-germanium layer extending over the silicon region, a gate electrode laterally extending over but being insulated from the silicon-germanium layer, a body region of the second conductivity type extending in the silicon-germanium layer and the silicon region, and source region of the first conductivity type extending in the silicon-germanium layer. The gate electrode laterally overlaps both the source and body regions such that a portion of the silicon germanium layer extending directly under the gate electrode between the source region and an outer boundary of the body region forms a channel region.
    Type: Application
    Filed: May 9, 2011
    Publication date: September 8, 2011
    Inventors: James Pan, Qi Wang
  • Patent number: 8001217
    Abstract: A system, a method and computer-readable media for distributing content to client devices over a network. Various items of content are stored in the network or available through the network such that a client device may request to receive an item of content over the network. The method selects items of content by anticipating which of the items users will request. The selected items of content are transmitted over the network in a group delivery to multiple client devices.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: August 16, 2011
    Assignee: Sprint Communications Company L.P.
    Inventors: James Pan, Claudio Lima, James Black
  • Patent number: 7994573
    Abstract: A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. The body regions form p-n junctions with the semiconductor region. Source regions of the second conductivity type extend over the body regions. The source regions form p-n junctions with the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric. A carbon-containing region extends in the semiconductor region below the body regions.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: August 9, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: James Pan
  • Publication number: 20110133275
    Abstract: A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.
    Type: Application
    Filed: February 15, 2011
    Publication date: June 9, 2011
    Inventor: James Pan
  • Patent number: 7951916
    Abstract: The present invention is directed to novel polypeptides having homology to the IL-1-like family of proteins and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention, and methods for producing the polypeptides of the present invention.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: May 31, 2011
    Assignee: Genentech, Inc.
    Inventors: Audrey Goddard, Guohua James Pan
  • Patent number: 7943993
    Abstract: A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a PN junction with the silicon region. A gate dielectric layer lines at least upper sidewalls of each trench, and insulates the gate electrode from the body region. Source regions of the first conductivity flank the trenches. A silicon-germanium region vertically extends through each source region and through a corresponding body region, and terminates within the corresponding body region before reaching the PN junction.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: May 17, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, Qi Wang
  • Patent number: 7936009
    Abstract: A shielded gate trench field effect transistor (FET) comprises trenches extending into a semiconductor region. A shield electrode is disposed in a bottom portion of each trench. The shield electrode is insulated from the semiconductor region by a shield dielectric. A gate electrode is disposed in each trench over the shield electrode, and an inter-electrode dielectric (IED) comprising a low-k dielectric extends between the shield electrode and the gate electrode.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: May 3, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, James J. Murphy
  • Patent number: 7932556
    Abstract: A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. Source regions of the second conductivity type extend over the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric layer. Contact openings extend into the body regions between adjacent gate electrodes. A seed layer extends along the bottom of each contact opening. The seed layer serves as a nucleation site for promoting growth of conductive fill material. A conductive fill material fills a lower portion of each contact opening. An interconnect layer fills an upper portion of each contact opening and is in direct contact with the conductive fill material. The interconnect layer is also in direct contact with corresponding source regions along upper sidewalls of the contact openings.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: April 26, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: James Pan
  • Patent number: 7910995
    Abstract: A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: March 22, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: James Pan