Abstract: A circuit is powered through a P-type transistor whose thermal instability behavior is to be evaluated. The threshold of the P-type transistor under evaluation and consequently the saturation current of the transistor are reflected in the frequency of the circuit, which in one embodiment is a ring oscillator. Additional circuitry is connected to the P-type transistor and the ring oscillator to ensure the proper stress conditions for the transistor and consequently to the evaluation of the P-type transistor.

Abstract: Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide. In an embodiment a capacitor device includes 10,000 layers of interleaved graphene separated by 9,999 layers of HfO. Odd layers of the graphene are electrically connected to a first terminal and even layers of graphene are electrically connected to a second terminal of the capacitor device.

Abstract: A system to enable detection of the process corner of each of the P and N devices of an SRAM array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-SRAM peripheral circuits and of read and write assist circuits for better handling of process distribution impact on circuits improving functionality and yield.

Abstract: In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.

Abstract: A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test.

Abstract: Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.

Abstract: Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed in sufficient thermal communication with the integrated circuit die so as to derive, from heat generated by the die, a voltage difference across first and second terminals of the thermoelectric generator structure. A powering structure is arranged to help power the integrated circuit, from the voltage difference across the first and second terminals of the thermoelectric generator. The thermoelectric generator can include IC packaging material that is made from thermoelectric semiconductor materials.

Abstract: A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew.

Abstract: Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide. In an embodiment a capacitor device includes 10,000 layers of interleaved graphene separated by 9,999 layers of HfO. Odd layers of the graphene are electrically connected to a first terminal and even layers of graphene are electrically connected to a second terminal of the capacitor device.

Abstract: In one well bias arrangement, no well bias voltage is applied to the n-well, and no well bias voltage is applied to the p-well. Because no external well bias voltage is applied, the n-well and the p-well are floating, even during operation of the devices in the n-well and the p-well. In another well bias arrangement, the lowest available voltage is not applied to the p-well, such as a ground voltage, or the voltage applied to the n+-doped source region of the n-type transistor in the p-well. This occurs even during operation of the n-type transistor in the p-well. In yet another well bias arrangement, the highest available voltage is not applied to the n-well, such as a supply voltage, or the voltage applied to the p+-doped source region of the p-type transistor in the n-well. This occurs even during operation of the p-type transistor in the n-well.

Abstract: An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel. An integrated circuit including the circuit is described.

Abstract: A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions.

Abstract: An automated circuitry that can co-exist in any chip and that allows for a accurate characterization of I*R drops at a block and/or whole chip level is described.

Abstract: Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide. In an embodiment a capacitor device includes 10,000 layers of interleaved graphene separated by 9,999 layers of HfO. Odd layers of the graphene are electrically connected to a first terminal and even layers of graphene are electrically connected to a second terminal of the capacitor device.

Abstract: Energy consumption is reduced within an Internet of Things (IoT) device, without degrading operating performance of the corresponding internal circuitry. A first internal supply voltage (VDDa) used to supply the internal circuitry is reduced from a VDD supply voltage to a lower voltage during an idle state, thereby reducing leakage currents in the internal circuitry. The first internal supply voltage (VDDa) may be reduced to a voltage that is one threshold voltage (Vtp) lower than the VDD supply voltage. A second internal supply voltage (VSSa) used to supply the internal circuitry is increased from the VSS supply voltage to a voltage higher than the VSS supply voltage during the idle state, thereby further reducing leakage currents in the internal circuitry. The second internal supply voltage (VSSa) may be increased to a voltage that is one threshold voltage (Vtn) higher than the VSS supply voltage.

Abstract: An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The number of nanowires or 2D material strips in the first set can be different from the number of nanowires or 2D material strips in the second set, so that the drive power of the individual transistors can be set with finer granularity.

Abstract: An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a plurality of transistors and an interconnect; wherein a transistor in the plurality has a channel comprising one or more nanowires or 2D material strips arranged in parallel, and the interconnect comprises one or more nanowires or 2D material strips arranged in parallel and connected to terminals of more than one of the transistors in the plurality of transistors. An integrated circuit including the plurality of transistors and the interconnect is described.

Abstract: An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel. An integrated circuit including the circuit is described.

Abstract: A sensor circuit is used to provide bit-cell read strength distribution of an SRAM array. A current-mirror circuit mirroring the bit-line current of an SRAM array is used to power the sensor circuit. A reference current representing nominal bit-cell read current is used as a reference. The current-mirror circuit senses the bit-line current. The current-mirror and the ring oscillator are not part of the bit-line read path.

Abstract: An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a plurality of transistors and an interconnect; wherein a transistor in the plurality has a channel comprising one or more nanowires or 2D material strips arranged in parallel, and the interconnect comprises one or more nanowires or 2D material strips arranged in parallel and connected to terminals of more than one of the transistors in the plurality of transistors. An integrated circuit including the plurality of transistors and the interconnect is described.