Patents by Inventor Jan Otterstedt
Jan Otterstedt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11907044Abstract: A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state. The evaluation unit is configured for evaluating the plurality of memory cells in the first state to obtain a first evaluation result, and for evaluating the plurality of memory cells in the second state to obtain a second evaluation result.Type: GrantFiled: September 13, 2021Date of Patent: February 20, 2024Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers
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Patent number: 11620507Abstract: An apparatus includes a sensor module. The sensor module includes an electromagnetic radiation sensor configured to provide electromagnetic radiation sensor data. The sensor module further includes a coded mask configured to modulate electromagnetic radiation incident to the electromagnetic radiation sensor and from which the electromagnetic radiation sensor data is generated. The apparatus further includes a computation module configured to obtain the electromagnetic radiation sensor data from the electromagnetic radiation sensor. The computation module is further configured to detect a property from the electromagnetic radiation sensor data using an artificial neural network. The computation module is further configured to output information related to the detected property via an output.Type: GrantFiled: May 18, 2018Date of Patent: April 4, 2023Assignee: Infineon Technologies AGInventor: Jan Otterstedt
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Publication number: 20220091914Abstract: A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state, wherein in the second state, at least one memory cell of the plurality of memory cells is connected to a different evaluation element to which the at least one memory cell is not connected in the first state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state.Type: ApplicationFiled: September 13, 2021Publication date: March 24, 2022Inventors: Jan OTTERSTEDT, Wolf ALLERS
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Patent number: 11231990Abstract: A device comprises an electronic data memory and a control unit configured to store a bit sequence in the electronic data memory as a stored bit sequence. The control unit is configured to check the stored bit sequence for bit errors, to generate error correction information having information about a correct bit value in the stored bit sequence, and to store the error correction information.Type: GrantFiled: November 19, 2019Date of Patent: January 25, 2022Assignee: INFINEON TECHNOLOGIES AGInventor: Jan Otterstedt
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Publication number: 20210312979Abstract: Read circuitry for a memory cell of a resistive change memory is suggested, wherein a signal of a bit-line that is connected to the memory cell is compared with a reference signal, and wherein the reference signal is determined based on a first dummy circuit that determines a leakage current of memory cells addressed by the bit-line. Also, a corresponding method is provided.Type: ApplicationFiled: March 31, 2021Publication date: October 7, 2021Inventors: Wolf Allers, Jan Otterstedt, Christian Peters
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Patent number: 11068344Abstract: A determination is made that error-correcting code functionality detected a first number of erroneous bits within a memory device. Bits within the memory device are evaluated to identify a subset of the bits as candidate bits. The candidate bits are evaluated to determine whether the error-correcting code functionality returns a non-error state, where no error correction is performed, based upon one or more combinations of candidate bits being inverted. Responsive to the error-correcting code functionality returning the non-error state for only one combination of the one or more combinations of candidate bits being inverted, the one combination of candidate bits is corrected.Type: GrantFiled: March 13, 2019Date of Patent: July 20, 2021Assignee: INFINEON TECHNOLOGIES AGInventors: Jan Otterstedt, Jayachandran Bhaskaran, Michael Goessel, Thomas Rabenalt
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Publication number: 20210217463Abstract: A position of a memory cell to be accessed within a memory field of a memory device is identified. A region associated with the memory field within which the position is located is identified. A compensation parameter comprising a fixed electric step value for the region is identified. The compensation parameter may be selected from a set of compensation parameters or may be calculated based upon the position of the memory cell. The compensation parameter is applied to an action performed on a line connected to the memory cell during the access of the memory cell.Type: ApplicationFiled: January 13, 2020Publication date: July 15, 2021Inventors: Jan OTTERSTEDT, Wolf ALLERS, Christian PETERS
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Patent number: 11062761Abstract: A position of a memory cell to be accessed within a memory field of a memory device is identified. A region associated with the memory field within which the position is located is identified. A compensation parameter comprising a fixed electric step value for the region is identified. The compensation parameter may be selected from a set of compensation parameters or may be calculated based upon the position of the memory cell. The compensation parameter is applied to an action performed on a line connected to the memory cell during the access of the memory cell.Type: GrantFiled: January 13, 2020Date of Patent: July 13, 2021Assignee: INFINEON TECHNOLOGIES AGInventors: Jan Otterstedt, Wolf Allers, Christian Peters
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Patent number: 10937469Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.Type: GrantFiled: October 29, 2019Date of Patent: March 2, 2021Assignee: INFINEON TECHNOLOGIES AGInventors: Jan Otterstedt, Robin Boch, Gerd Dirscherl, Bernd Meyer, Christian Peters, Steffen Sonnekalb
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Publication number: 20200293402Abstract: A determination is made that error-correcting code functionality detected a first number of erroneous bits within a memory device. Bits within the memory device are evaluated to identify a subset of the bits as candidate bits. The candidate bits are evaluated to determine whether the error-correcting code functionality returns a non-error state, where no error correction is performed, based upon one or more combinations of candidate bits being inverted. Responsive to the error-correcting code functionality returning the non-error state for only one combination of the one or more combinations of candidate bits being inverted, the one combination of candidate bits is corrected.Type: ApplicationFiled: March 13, 2019Publication date: September 17, 2020Inventors: Jan OTTERSTEDT, Jayachandran BHASKARAN, Michael GOESSEL, Thomas RABENALT
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Patent number: 10776259Abstract: A method for data processing is disclosed. A blank state is determined for several data bits based on a majority decision. Each data bit is represented by a group of at least two memory cells. The at least two memory cells of this group are complementary cells of a differential read memory.Type: GrantFiled: October 31, 2013Date of Patent: September 15, 2020Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Thomas Kern
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Publication number: 20200159613Abstract: A device comprises an electronic data memory and a control unit configured to store a bit sequence in the electronic data memory as a stored bit sequence. The control unit is configured to check the stored bit sequence for bit errors, to generate error correction information having information about a correct bit value in the stored bit sequence, and to store the error correction information.Type: ApplicationFiled: November 19, 2019Publication date: May 21, 2020Inventor: Jan OTTERSTEDT
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Patent number: 10628084Abstract: A memory arrangement having a memory cell field with columns and rows of writable memory cells, a memory controller which is configured to initiate an access to a first group of memory cells of a row of memory cells and, together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells, and a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.Type: GrantFiled: October 10, 2018Date of Patent: April 21, 2020Assignee: Infineon Technologies AGInventors: Joel Hatsch, Bernd Meyer, Jan Otterstedt, Steffen Sonnekalb
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Publication number: 20200066312Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.Type: ApplicationFiled: October 29, 2019Publication date: February 27, 2020Inventors: Jan OTTERSTEDT, Robin BOCH, Gerd DIRSCHERL, Bernd MEYER, Christian PETERS, Steffen SONNEKALB
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Patent number: 10497408Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.Type: GrantFiled: December 5, 2017Date of Patent: December 3, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Jan Otterstedt, Robin Boch, Gerd Dirscherl, Bernd Meyer, Christian Peters, Steffen Sonnekalb
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Patent number: 10475520Abstract: A memory circuit includes electrically programmable memory cells arranged in a non-volatile memory cell array along rows and columns, word lines, each word line coupled with one or more memory cells, non-volatile marking memory cells, wherein at least one word line of the word lines is associated with one or more marking memory cells, and marking bit lines, each associated with marking memory cells, marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.Type: GrantFiled: November 24, 2017Date of Patent: November 12, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Jan Otterstedt, Robin Boch, Gerd Dirscherl, Bernd Meyer, Christian Peters, Steffen Sonnekalb
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Publication number: 20190114111Abstract: A memory arrangement having a memory cell field with columns and rows of writable memory cells, a memory controller which is configured to initiate an access to a first group of memory cells of a row of memory cells and, together with the access to the first group of memory cells, to initiate a read access to a second group of memory cells of the row of memory cells, and a verification circuit which is configured to check whether the access to the first group of memory cells has been performed on the correct row of memory cells on the basis of whether values read during the read access to the second group of memory cells match values previously stored by the second group of memory cells.Type: ApplicationFiled: October 10, 2018Publication date: April 18, 2019Inventors: Joel Hatsch, Bernd Meyer, Jan Otterstedt, Steffen Sonnekalb
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Patent number: 10261899Abstract: A method for data processing including mapping between a logical address and a physical address of a memory, wherein the memory comprises several pages, wherein a group of pages comprises at least one page that comprises at least two portions, and wherein the at least two portions of each page of the group are not part of a single-page logical address space.Type: GrantFiled: September 3, 2014Date of Patent: April 16, 2019Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Stefan Rueping
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Patent number: 10157095Abstract: In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.Type: GrantFiled: April 19, 2017Date of Patent: December 18, 2018Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Michael Gössel, Thomas Rabenalt, Thomas Kern
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Publication number: 20180341858Abstract: An apparatus includes a sensor module. The sensor module includes an electromagnetic radiation sensor configured to provide electromagnetic radiation sensor data. The sensor module further includes a coded mask configured to modulate electromagnetic radiation incident to the electromagnetic radiation sensor and from which the electromagnetic radiation sensor data is generated. The apparatus further includes a computation module configured to obtain the electromagnetic radiation sensor data from the electromagnetic radiation sensor. The computation module is further configured to detect a property from the electromagnetic radiation sensor data using an artificial neural network. The computation module is further configured to output information related to the detected property via an output.Type: ApplicationFiled: May 18, 2018Publication date: November 29, 2018Applicant: Infineon Technologies AGInventor: Jan OTTERSTEDT