Abstract: Non volatile memories and methods of programming thereof are disclosed. In one embodiment, the method of programming a memory array includes receiving a series of data blocks, each data block having a number of bits that are to be programmed, determining the number of bits that are to be programmed in a first data block, determining the number of bits that are to be programmed in a second data block, and writing the first data block and the second data block into the memory array in parallel if the sum of the number of bits that are to be programmed in the first data block and the second data block is not greater than a maximum value. The first and second data blocks may or may not be adjacent data blocks. Improved programming efficiency may be achieved in a memory circuit when the maximum allowable current may be limited by the application or the size of a charge pump. Inverse data may be written in parallel if the sum is greater than the maximum value.

Abstract: A structure and method for increasing the operating speed and reducing the overall programming time of a memory array are provided herein. The method and structure reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). The write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit, allowing a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) and reducing overall memory write time.

Abstract: A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse parameters each having a fixed valued, and determining a fail count by measuring the number of non-volatile memory cells of the plurality of non-volatile memory cells having a storage parameter level exceeding a verify level. The method further includes determining a change in an programming behavior of the plurality of non-volatile memory cells based on the fail count, adjusting a value of at least one pulse parameter of at least one second programming pulse defined by the plurality of pulse parameters to a desired value based on the change in programming behavior, and applying the at least one second programming pulse to the plurality non-volatile memory cells.

Abstract: A device for protecting a data word against data corruption includes first and second determiners. The first determiner is configured to determine an error correction code cvA associated with a data word a so that cvA=aAT, with A being a generator matrix of a linear systematic base correction code, the columns of which enable performance of an x-bit error correction on replica of the data word a and the associated error correction code cvA. The second determiner is configured to determine an extended error correction code cvE so that (cvA|cvE)=aFT, with F being an extended generator matrix F = ( A E ) of an extended linear systematic correction code, the columns of which enable, using the extension error correction code cvE, performance of an y-bit error correction, with y>x, on a replica of the data word a and the associated error correction code cvA.

Abstract: Some aspects of the present disclosure relate to a read circuit that uses a hybrid read scheme as set forth herein. In this hybrid read scheme, a state machine, at a first time in the read operation, sets a reference signal SRef to a first reference value to induce determination of a first comparison result. At a second subsequent time in the read operation, the state machine sets the reference signal SRef to a second reference value, which is based on the first comparison result. Setting the reference signal to the second reference value induces determination of a second comparison result. The first and second comparison results are then used to determine the digital value read from the memory cell.

Abstract: In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.

Abstract: In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.

Abstract: One or more embodiments are related to a method of operating a phase-change memory array, including: providing the phase-change memory array, the phase-change memory array including a phase-change memory element in series with an access device between a first address line and a power line; causing a first current through the memory element from the first address line to the power line; and causing a second current through the memory element from the power line to the first address line.

Abstract: The disclosed invention provides a structure and method for increasing the operating speed and reduce the overall programming time of a memory array. In one embodiment, the method and structure provided herein reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). Specifically, the write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit. This interleaving of data bit write windows allows a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) reducing overall memory write time.

Abstract: A method of operating an integrated circuit includes determining a resistance value of at least one resistivity-changing memory cell when the memory cell is in a low-resistance state, the at least one resistivity-changing memory cell configured to be programmable to at least the low-resistance state and a high-resistance state, comparing the resistance value to a threshold value, selecting, based on the comparison, a cell reset process to be employed for programming the at least one resistivity-changing memory cell to the high-resistance state. The selecting includes selecting a predetermined reset process as the cell reset process when the resistance value is less than the threshold value, and adjusting the predetermined process and selecting the adjusted predetermined reset process as the cell reset process when the resistance value is at least equal to the threshold value.

Abstract: A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse parameters each having a fixed valued, and determining a fail count by measuring the number of non-volatile memory cells of the plurality of non-volatile memory cells having a storage parameter level exceeding a verify level. The method further includes determining a change in an programming behavior of the plurality of non-volatile memory cells based on the fail count, adjusting a value of at least one pulse parameter of at least one second programming pulse defined by the plurality of pulse parameters to a desired value based on the change in programming behavior, and applying the at least one second programming pulse to the plurality non-volatile memory cells.

Abstract: A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read voltage. The voltage comparator is adapted to compare a voltage of the memory cell with a reference voltage after the provision of the selectable voltage to the memory cell. The memory cell retains data when the memory cell voltage generated at least in part by the test voltage is substantially equal to the reference voltage.

Abstract: A method and flash memory device that correct over-erased memory cells are described. The device includes flash memory cells, erase circuitry, measuring circuitry, and a pulse generator. The method includes performing an erase operation on a first plurality of memory cells, measuring at least one memory cell of a second plurality of memory cells, and if an over-erased memory cell is detected in measuring the second plurality of cells, applying one or more programming pulses to the one or more over-erased cells, the one or more programming pulses cumulatively sufficient to correct a cell in a maximum over-erased state. Also described is a method that registers over-erased cells for programming and applies one or more programming pulses to the registered over-erased cells, the one or more programming pulses cumulatively sufficient to correct a cell in a maximum over-erased state.

Abstract: In one embodiment, a bit-line interface is disclosed. The bit-line interface has a multiplexer having a plurality of bit-line outputs, and a write path coupled to a multiplexer signal input. The bit-line interface also has a read path coupled to the multiplexer signal input, wherein the read path and the write path share at least one component.

Abstract: An embodiment of the invention relates to a memory device and a related method. In an embodiment, a check matrix for an error-correcting code is formed so that sets of input data bits can be written, wherein each set of input data bits generates one set of error-correcting code bits that can be written independently of each other and in an arbitrary order. An error-correcting code is thereby produced without the need to erase or copy any existing, originally written bit upon presentation of new input data.

Abstract: The invention relates to a data processing device with a functionally programmable logic circuit and a programming interface. An authorization control unit is provided, which protects the programming interface against an unauthorized access. This enables the functions of a semiconductor module to be changed in a customer-specific manner while preventing unauthorized entities from subsequently changing the functionality.

Abstract: Non volatile memories and methods of programming thereof are disclosed. In one embodiment, the method of programming a memory array includes receiving a series of data blocks, each data block having a number of bits that are to be programmed, determining the number of bits that are to be programmed in a first data block, determining the number of bits that are to be programmed in a second data block, and writing the first and the second data blocks into a memory array in parallel if the sum of the number of bits that are to be programmed in the first data block and the second data block is not greater than a maximum value.

Abstract: A method of operating an integrated circuit includes determining a resistance value of at least one resistivity-changing memory cell when the memory cell is in a low-resistance state, the at least one resistivity-changing memory cell configured to be programmable to at least the low-resistance state and a high-resistance state, comparing the resistance value to a threshold value, selecting, based on the comparison, a cell reset process to be employed for programming the at least one resistivity-changing memory cell to the high-resistance state. The selecting includes selecting a predetermined reset process as the cell reset process when the resistance value is less than the threshold value, and adjusting the predetermined process and selecting the adjusted predetermined reset process as the cell reset process when the resistance value is at least equal to the threshold value.

Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

Abstract: A device for non-volatile storage of a status value indicating that there has been a condition, including a non-volatile storage, an energy storage for storing energy when applying a supply voltage, and a switching circuit to couple the energy storage to the non-volatile storage to write the status value thereto if the condition is present.