Abstract: Data processing apparatus having an execution unit, a flow controller having a program counter, and a program counter sensor, which is connected to a data bus and to the program counter. The program counter sensor has a logic unit that ascertains the address of an instruction which is to be executed next from data transferred via the data bus, and a comparator, which compares the ascertained address with a content of the program counter and triggers an alarm signal if there is any discrepancy.

Abstract: A multi-level sensing scheme compares the state of a multi-level storage cell with monotonously changing reference states, which are associated to different information values. That particular information value is identified to be the information stored in the multi-level storage cell, which has associated that reference state which, in a changing direction, firstly exceeds the state.

Abstract: A memory circuit having a plurality of memory areas, whose order depends on respectively associated logical addresses, and which each have an associated control value, and a control means, which is designed such that the same assigns a value to a control value associated with a target memory area when writing into the same, which corresponds to the value of a lowest used memory area, when one exists, and assigns the same an arbitrary or predetermined value, when none exists, and when a predetermined condition is fulfilled, and when at least two used memory areas exist, rewrites the content of a next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, and changes the control value of this memory area, when the same exists, or rewrites a content of the lowest memory area and changes the associated control value, when the next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, does not exist.

Abstract: A data retention monitor for a memory cell including a voltage source and a voltage comparator. The voltage source is adapted to provide a selectable voltage to the memory cell. The selectable voltage includes a read voltage and a test voltage, with the test voltage being greater than the read voltage. The voltage comparator is adapted to compare a voltage of the memory cell with a reference voltage after the provision of the selectable voltage to the memory cell. The memory cell retains data when the memory cell voltage generated at least in part by the test voltage is substantially equal to the reference voltage.

Abstract: A method of operating a phase-change memory array. The method may comprise causing a first current to flow through a phase-change memory element in a first direction and causing a second current to flow through the memory element in a second direction.

Abstract: A multi-level sensing scheme compares the state of a multi-level storage cell with monotonously changing reference states, which are associated to different information values. That particular information value is identified to be the information stored in the multi-level storage cell, which has associated that reference state which, in a changing direction, firstly exceeds the state.

Abstract: A memory circuit having a plurality of memory areas, whose order depends on respectively associated logical addresses, and which each have an associated control value, and a control means, which is designed such that the same assigns a value to a control value associated with a target memory area when writing into the same, which corresponds to the value of a lowest used memory area, when one exists, and assigns the same an arbitrary or predetermined value, when none exists, and when a predetermined condition is fulfilled, and when at least two used memory areas exist, rewrites the content of a next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, and changes the control value of this memory area, when the same exists, or rewrites a content of the lowest memory area and changes the associated control value, when the next memory area, whose control value has a predetermined relation to the control value of the lowest memory area, does not exist.

Abstract: A device for non-volatile storage of a status value indicating that there has been a condition, including a non-volatile storage, an energy storage for storing energy when applying a supply voltage, and a switching circuit to couple the energy storage to the non-volatile storage to write the status value thereto if the condition is present.

Abstract: A configurable logic circuit having a plurality of logic blocks and a connecting structure, via which the logic blocks are interconnectable, wherein the logic blocks are implemented in dual rail technique.

Abstract: Data processing apparatus having an execution unit, a flow controller having a program counter, and a program counter sensor, which is connected to a data bus and to the program counter. The program counter sensor has a logic unit that ascertains the address of an instruction which is to be executed next from data transferred via the data bus, and a comparator, which compares the ascertained address with a content of the program counter and triggers an alarm signal if there is any discrepancy.

Abstract: The invention relates to a method for protecting data during a self-test of a microcontrollers, in which all of the circuit elements within the microcontroller can be tested, where the course of the self-test cannot be altered via the external pins, and no intermediate results are passed to the outside via the pins. The invention also relates to an configuration in the form of an integrated circuit which can be used to implement the method, and to correspondingly equipped microcontrollers.

Abstract: The invention relates to a data processing device with a functionally programmable logic circuit and a programming interface. An authorization control unit is provided, which protects the programming interface against an unauthorized access. This enables the functions of a semiconductor module to be changed in a customer-specific manner while preventing unauthorized entities from subsequently changing the functionality.

Abstract: The invention is directed to a protective circuit for an integrated circuit 1. This protective circuit is preferably arranged in a plurality of circuit levels 2, 3 under and/or above the intergrated circuit 1. It exhibits a plurality of interconnects 10, 11 that are charged with different signals of one or more signal generators. The different signals, after traversing the interconnects 10, 11, are analyzed with one or more detectors in that the signals received by detectors are respectively compared to rated reference signals, and an alarm signal is forwarded to the integrated circuit given the presence of a significant difference. On the basis of this alarm signal, the integrated circuit is switched into a security mode that makes an analysis or a manipulation of the integrated circuit practically impossible.

Abstract: The invention relates to a method for protecting data during a self-test of a microcontrollers, in which all of the circuit elements within the microcontroller can be tested, where the course of the self-test cannot be altered via the external pins, and no intermediate results are passed to the outside via the pins. The invention also relates to an configuration in the form of an integrated circuit which can be used to implement the method, and to correspondingly equipped microcontrollers.