Patents by Inventor Jan Willem Maes

Jan Willem Maes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190163056
    Abstract: The method relates to a method of forming an enhanced unexposed photoresist layer from an unexposed photoresist layer on a substrate by increasing the sensitivity of the unexposed photoresist to exposure radiation. The method comprises: providing the substrate with the unexposed photoresist layer in a reaction chamber; providing a first precursor comprising a portion of a photosensitizer sensitive to exposure radiation in the reaction chamber; and, infiltrating the unexposed photoresist layer on the substrate with the first precursor.
    Type: Application
    Filed: October 22, 2018
    Publication date: May 30, 2019
    Inventors: Jan Willem Maes, Krzysztof Kamil Kachel, David Kurt de Roest
  • Publication number: 20190157086
    Abstract: A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer.
    Type: Application
    Filed: January 23, 2019
    Publication date: May 23, 2019
    Inventors: Jan Willem MAES, Werner KNAEPEN, Roel GRONHEID, Arjun SINGH
  • Publication number: 20190155159
    Abstract: A method of forming a directed self-assembled (DSA) layer on a substrate by: providing a substrate; applying a layer comprising a self-assembly material on the substrate; and annealing of the self-assembly material of the layer to form a directed self-assembled layer by providing a controlled temperature and gas environment around the substrate. The controlled gas environment comprises molecules comprising an oxygen element with a partial pressure between 10-2000 Pa.
    Type: Application
    Filed: April 7, 2017
    Publication date: May 23, 2019
    Inventors: Werner Knaepen, Jan Willem Maes, Maarten Stokhof, Roel Gronheid, Hari Pathangi Sriraman
  • Publication number: 20190103266
    Abstract: Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl3, antimony alkylamines, and antimony alkoxides, such as Sb(OEt)3. The oxygen source may be, for example, ozone. In some embodiments the antimony oxide thin films are deposited in a batch reactor. The antimony oxide thin films may serve, for example, as etch stop layers or sacrificial layers.
    Type: Application
    Filed: August 20, 2018
    Publication date: April 4, 2019
    Inventors: Raija H. Matero, Linda Lindroos, Hessel Sprey, Jan Willem Maes, David de Roest, Dieter Pierreux, Kees van der Jeugd, Lucia D'Urzo, Tom E. Blomberg
  • Publication number: 20190103303
    Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.
    Type: Application
    Filed: October 12, 2018
    Publication date: April 4, 2019
    Inventors: Han Wang, Qi Xie, Delphine Longrie, Jan Willem Maes, David de Roest, Julian Hsieh, Chiyu Zhu, Timo Asikainen, Krzysztof Kachel, Harald Profijt
  • Publication number: 20190088555
    Abstract: A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.
    Type: Application
    Filed: September 18, 2017
    Publication date: March 21, 2019
    Inventors: Qi Xie, Chiyu Zhu, Kiran Shrestha, Pauline Calka, Oreste Madia, Jan Willem Maes, Michael Eugene Givens
  • Publication number: 20190055643
    Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.
    Type: Application
    Filed: July 20, 2018
    Publication date: February 21, 2019
    Inventors: Delphine Longrie, Antti Juhani Niskanen, Han Wang, Qi Xie, Jan Willem Maes, Shang Chen, Toshiharu Watarai, Takahiro Onuma, Dai Ishikawa, Kunitoshi Namba
  • Patent number: 10204782
    Abstract: A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: February 12, 2019
    Assignees: IMEC vzw, ASM IP HOLDING B.V.
    Inventors: Jan Willem Maes, Werner Knaepen, Roel Gronheid, Arjun Singh
  • Patent number: 10199213
    Abstract: In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: February 5, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Suvi P. Haukka, Fu Tang, Michael E. Givens, Jan Willem Maes, Qi Xie
  • Publication number: 20190006586
    Abstract: Methods are provided for depositing doped chalcogenide films. In some embodiments the films are deposited by vapor deposition, such as by atomic layer deposition (ALD). In some embodiments a doped GeSe film is formed. The chalcogenide film may be doped with carbon, nitrogen, sulfur, silicon, or a metal such as Ti, Sn, Ta, W, Mo, Al, Zn, In, Ga, Bi, Sb, As, V or B. In some embodiments the doped chalcogenide film may be used as the phase-change material in a selector device.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 3, 2019
    Inventors: Jan Willem Maes, Suvi Haukka
  • Patent number: 10141189
    Abstract: In some embodiments, a compound semiconductor is formed by diffusion of semiconductor species from a source semiconductor layer into semiconductor material in a substrate. The source semiconductor layer may be an amorphous or polycrystalline structure, and provides a source of semiconductor species for later diffusion into the other semiconductor material. Advantageously, such a semiconductor layer may be more conformal than an epitaxially grown, crystalline semiconductor layer. As a result, this more conformal semiconductor layer acts as a uniform source of the semiconductor species for diffusion into the semiconductor material in the substrate. In some embodiments, an interlayer is formed between the source semiconductor layer and the substrate, and then the interlayer is trimmed before depositing the source semiconductor layer. In some other embodiments, the source semiconductor layer is deposited directly on the substrate, and has an amorphous or polycrystalline structure.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: November 27, 2018
    Assignee: ASM IP HOLDING B.V.
    Inventors: Harald Profijt, Qi Xie, Jan Willem Maes, David Kohen
  • Patent number: 10121699
    Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: November 6, 2018
    Assignee: ASM IP HOLDING B.V.
    Inventors: Han Wang, Qi Xie, Delphine Longrie, Jan Willem Maes, David de Roest, Julian Hsieh, Chiyu Zhu, Timo Asikainen, Krzysztof Kachel, Harald Profijt
  • Publication number: 20180308686
    Abstract: A method for improving source/drain performance through conformal solid state doping and its resulting device are disclosed. Specifically, the doping takes place through an atomic layer deposition of a dopant layer. Embodiments of the invention may allow for an increased doping layer, improved conformality, and reduced defect formation, in comparison to alternate doping methods, such as ion implantation or epitaxial doping.
    Type: Application
    Filed: June 26, 2018
    Publication date: October 25, 2018
    Inventors: Qi Xie, David de Roest, Jacob Woodruff, Michael Eugene Givens, Jan Willem Maes, Timothee Blanquart
  • Patent number: 10056249
    Abstract: Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl3, antimony alkylamines, and antimony alkoxides, such as Sb(OEt)3. The oxygen source may be, for example, ozone. In some embodiments the antimony oxide thin films are deposited in a batch reactor. The antimony oxide thin films may serve, for example, as etch stop layers or sacrificial layers.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: August 21, 2018
    Assignee: ASM International N.V.
    Inventors: Raija H. Matero, Linda Lindroos, Hessel Sprey, Jan Willem Maes, David de Roest, Dieter Pierreux, Kees van der Jeugd, Lucia D'Urzo, Tom E. Blomberg
  • Publication number: 20180233350
    Abstract: Methods for selective deposition, and structures thereof, are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. A passivation layer is selectively formed from vapor phase reactants on the first surface while leaving the second surface without the passivation layer. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the passivation layer. The first surface can be metallic while the second surface is dielectric, or the second surface is dielectric while the second surface is metallic. Accordingly, material, such as a dielectric, can be selectively deposited on either metallic or dielectric surfaces relative to the other type of surface using techniques described herein. Techniques and resultant structures are also disclosed for control of positioning and shape of layer edges relative to boundaries between underlying disparate materials.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 16, 2018
    Inventors: Eva E. Tois, Suvi P. Haukka, Raija H. Matero, Elina Färm, Delphine Longrie, Hidemi Suemori, Jan Willem Maes, Marko Tuominen, Shaoren Deng, Ivo Johannes Raaijmakers, Andrea Illiberi
  • Patent number: 10041166
    Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 7, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Delphine Longrie, Antti Juhani Niskanen, Han Wang, Qi Xie, Jan Willem Maes, Shang Chen, Toshiharu Watarai, Takahiro Onuma, Dai Ishikawa, Kunitoshi Namba
  • Patent number: 10032628
    Abstract: A method for improving source/drain performance through conformal solid state doping and its resulting device are disclosed. Specifically, the doping takes place through an atomic layer deposition of a dopant layer. Embodiments of the invention may allow for an increased doping layer, improved conformality, and reduced defect formation, in comparison to alternate doping methods, such as ion implantation or epitaxial doping.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 24, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Qi Xie, David de Roest, Jacob Woodruff, Michael Eugene Givens, Jan Willem Maes, Timothee Blanquart
  • Publication number: 20180190793
    Abstract: In some embodiments, a compound semiconductor is formed by diffusion of semiconductor species from a source semiconductor layer into semiconductor material in a substrate. The source semiconductor layer may be an amorphous or polycrystalline structure, and provides a source of semiconductor species for later diffusion into the other semiconductor material. Advantageously, such a semiconductor layer may be more conformal than an epitaxially grown, crystalline semiconductor layer. As a result, this more conformal semiconductor layer acts as a uniform source of the semiconductor species for diffusion into the semiconductor material in the substrate. In some embodiments, an interlayer is formed between the source semiconductor layer and the substrate, and then the interlayer is trimmed before depositing the source semiconductor layer. In some other embodiments, the source semiconductor layer is deposited directly on the substrate, and has an amorphous or polycrystalline structure.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventors: Harald Profijt, Qi Xie, Jan Willem Maes, David Kohen
  • Publication number: 20180171475
    Abstract: A sequential infiltration synthesis apparatus comprising: a reaction chamber constructed and arranged to hold at least a first substrate; a precursor distribution and removal system to provide to and remove from the reaction chamber a vaporized first or second precursor; and, a sequence controller operably connected to the precursor distribution and removal system and comprising a memory provided with a program to execute infiltration of an infiltrateable material provided on the substrate when run on the sequence controller by: activating the precursor distribution and removal system to provide and maintain the first precursor for a first period T1 in the reaction chamber; activating the precursor distribution and removal system to remove a portion of the first precursor from the reaction chamber for a second period T2; and, activating the precursor distribution and removal system to provide and maintain the second precursor for a third period T3 in the reaction chamber.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 21, 2018
    Inventors: Jan Willem Maes, Werner Knaepen, Krzysztof Kamil Kachel, David Kurt De Roest, Bert Jongbloed, Dieter Pierreux
  • Publication number: 20180174826
    Abstract: The disclosure relates to a sequential infiltration synthesis apparatus comprising: a reaction chamber constructed and arranged to accommodate at least one substrate; a first precursor flow path to provide the first precursor to the reaction chamber when a first flow controller is activated; a second precursor flow path to provide a second precursor to the reaction chamber when a second flow controller is activated; a removal flow path to allow removal of gas from the reaction chamber; a removal flow controller to create a gas flow in the reaction chamber to the removal flow path when the removal flow controller is activated; and, a sequence controller operably connected to the first, second and removal flow controllers and the sequence controller being programmed to enable infiltration of an infiltrateable material provided on the substrate in the reaction chamber. The apparatus may be provided with a heating system.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 21, 2018
    Inventors: Ivo Johannes Raaijmakers, Jan Willem Maes, Werner Knaepen, Krzysztof Kamil Kachel